Effect of magnesium oxide passivation on the performance of amorphous indium-gallium-zinc-oxide thin film transistors

Effect of hygroscopic magnesium oxide (MgO) passivation layer on the stability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress and positive bias temperature stress has been investigated. The effect of MgO passivation has been observed by comparing the shift of the positive threshold voltage (V_th) after constant bias temperature stress, which were 8.2 V for the unpassivated TFTs and 1.88 V for the passivated TFTs.In addition, MgO passivated a-IGZO TFTs show also excellent stability under a humidity test since MgO passivation layer can prevent the penetration of water into back channel. In order to investigate the origin of humidity test result, we have measured X-ray photoelectron spectroscopy depth profile of both unpassivated and MgO passivated TFTs with a-IGZO back channel layers after N₂ wet annealing.     

Effect of gallium content on bias stress stability of solution-deposited Ga-Sn-Zn-O semiconductor transistors

We generated solution-processed thin film transistor (TFTs) using gallium tin zinc oxide (GTZO, Ga-Sn-Zn-O) layers as the channel that exhibit improved bias-stress stability during device operation under ambient conditions. The cause of the bias-stress stability was investigated through comparisons with zinc tin oxide (ZTO, Zn-Sn-O)-based TFTs, which suffer red from bias stress instability. Based on in-depth analysis of the electrical characteristics and chemical structure of both GTZO and ZTO layers, it was discovered that the GTZO layers had a significantly lower oxygen vacancy concentration than did the ZTO layer, which influenced the electrical performance of the GTZO transistors as well as their bias-stress stability. When 5 mol% gallium was added, a bias stress-stable transistor was obtained, exhibiting typical semiconductor behavior with a field-effect mobility of 1.2 cm² V^− 1 s^− 1, on/off ratio of 10⁶, off-current of 1 × 10^− 10 A, and threshold voltage of 19.6 V. Further doping of Ga deteriorated the device performance, which was found to be associated with decreased carrier concentration and segregation of an insulating secondary phase.     

High-performance amorphous indium-gallium-zinc oxide thin-film transistors with polymer gate dielectric

The fabrication of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a spin-coated polymer gate dielectric on a glass substrate is reported. The interface state density at the poly(4-vinylphenol)/a-IGZO interface is only around 4.05 × 10¹¹ cm^− 2. The TFTs' threshold voltage, subthreshold swing, on-off current ratio, and carrier mobility are 2.6 V, 1.3 V/decade, 1 × 10⁵, and 21.8 cm²/V s, respectively. These characteristics indicate that the TFTs are suitable for use as nonvolatile memory devices and in flexible electronic applications.     

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V_GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10¹¹ cm^− 2, needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.     

Comparison of a-Si TFTs fabricated by Cat-CVD and PECVD methods

We investigate the characteristics of amorphous silicon thin film transistors (a-Si TFTs) fabricated by plasma-enhanced chemical vapor deposition (PECVD) and catalytic CVD (Cat-CVD), and their stability under bias and temperature (BT) accelerated stress. The Cat-CVD a-Si TFTs have off-leak current as small as 10^− 14 A, and a smaller threshold voltage shift under the BT stress. The superiority in off-leak current and stability is observed in the Cat-CVD a-Si TFTs fabricated at both 320 °C and 180 °C. The high performance and stability of the Cat-CVD a-Si TFTs will enable to use low-cost glass substrates and result in a cost reduction of TFT fabrication.     

Oligomer semiconductor/dielectric interface modification for organic thin film transistor hysteresis reduction

In this work, we investigate the hydroxyl group effect on hysteresis of the low voltage organic thin film transistor (OTFT). A high k material, hafnium oxide, is utilized as gate dielectric to reduce OTFT operational voltage. By using the hydroxyl-free polymer, polystyrene, the hydroxyl groups on hafnium oxide surface will be shielded. The modification at semiconductor/dielectric interface prevents accumulated charges from trapping in surface states. Such a polymer coverage layer reduces hysteresis and suppresses the off current as low as 10⁻¹¹ A. The interface traps resulted from ambient water absorption significantly decrease according to the hysteresis cancellation. By stacking polystyrene on hafnium oxide, the pentacene-based OTFT shows the threshold voltage of − 2.2 V, on/off current ratio of 10⁵, subthreshold swing of 0.34 V/dec, and mobility of 0.24 cm²/V s under operational voltage of 10 V.     

Amorphous structure and electrical performance of low-temperature annealed amorphous indium zinc oxide transparent thin film transistors

The effect of low-temperature (200 °C) annealing on the threshold voltage, carrier density, and interface defect density of amorphous indium zinc oxide (a-IZO) thin film transistors (TFTs) is reported. Transmission electron microscopy and x-ray diffraction analysis show that the amorphous structure is retained after 1 h at 200 °C. The TFTs fabricated from as-deposited IZO operate in the depletion mode with on-off ratio of > 10⁶, sub-threshold slope (S) of ~ 1.5 V/decade, field effect mobility (μ_FE) of 18 ± 1.6 cm²/Vs, and threshold voltage (V_Th) of − 3 ± 0.7 V. Low-temperature annealing at 200 °C in air improves the on-current, decreases the sub-threshold slope (1.56 vs. 1.18 V/decade), and increases the field effect mobility (μ_FE) from 18.2 to 23.3 cm²/Vs but also results in a V_Th shift of − 15 ± 1.1 V. The carrier density in the channel of the as-deposited (4.3 × 10¹⁶ /cm³) and annealed at 200 °C (8.1 × 10¹⁷ /cm³) devices were estimated from test-TFT structures using the transmission line measurement methods to find channel resistivity at zero gate voltage and the TFT structures to estimate carrier mobility.     

Wet etching rates of InGaZnO for the fabrication of transparent thin-film transistors on plastic substrates

The wet etch process for amorphous indium gallium zinc oxide (a-IGZO or a-InGaZnO) by using various etchants is reported. The etch rates of a-IGZO, compared to another indium-based oxides including indium gallium oxide (IGO), indium zinc oxide (IZO), and indium tin oxide (ITO), are measured by using acetic acid, citric acid, hydrochloric acid, perchloric acid, and aqua ammonia as etchants, respectively. In our experimental results, the etch rate of the transparent oxide semiconductor (TOS) films by using acid solutions ranked accordingly from high to low are IZO, IGZO, IGO and ITO. Comparatively, the etch rate of the TOS films by using alkaline ammonia solution ranked from high to low are IGZO, IZO, IGO and ITO, in that order.Using the proposed wet etching process with high etch selectivity, bottom-gate-type thin-film transistors (TFTs) based on a-IGZO channels and Y₂O₃ gate-insulators were fabricated by radio-frequency sputtering on plastic substrates. The wet etch processed TFT with 30 µm gate length and 120 µm gate width exhibits a saturation mobility of 46.25 cm² V^− 1 s^− 1, a threshold voltage of 1.3 V, a drain current on-off ratio > 10⁶ , and subthreshold gate voltage swing of 0.29 V decade^− 1. The performance of the TFTs ensures the applicability of the wet etching process for IGZO to electronic devices on organic polymer substrates.     

Threshold voltage shift by controlling Ga in solution processed Si-In-Zn-O thin film transistors

The threshold voltage change of solution processed gallium-silicon-indium-zinc oxide (GSIZO) thin film transistors (TFTs) annealed at 200 °C has been investigated depending on gallium ratio. GSIZO thin films were formed with various gallium ratios from 0.01 to 1 M ratio. The 30 nm-thick GSIZO film exhibited optimized electrical characteristics, such as field effect mobility (μ_FE) of 2.2 × 10^− 2 cm²/V·s, subthreshold swing (S.S) of 0.11 V/dec, and on/off current ratio (I_on/off) of above 10⁵. The variation of gallium metal cation has an effect on the threshold voltage (V_th) and the field effect mobility (μ_FE). The V_th was shifted toward positive direction from − 5.2 to − 0.4 V as increasing gallium ratio, and μ_FE was decreased from 2.2 × 10^− 2 to 5 × 10^− 3 cm²/V s. These results indicated that gallium was acted as carrier suppressor by degenerating oxygen vacancy. The electrical property of GSIZO TFTs has been analyzed as a function of the gallium ratio in SIZO system, and it clearly showed that variation of gallium contents could change on the performance of TFTs.     

Effects of low-temperature ozone annealing on operation characteristics of amorphous In-Ga-Zn-O thin-film transistors

Effects of low-temperature annealing were examined for amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs). In a previous study, we reported that O₂ annealing is effective to improve performances of a-IGZO TFTs when annealed at ≥ 300 °C, but causes large negative threshold voltage shift when annealed at ≤ 200 °C. Here, we examined effects of ozone (O₃) annealing on physical properties and TFT characteristics of a-IGZO in comparison with conventional O₂ annealing. We found little differences in chemical composition, band gap and photoemission spectra between the O₂ and the O₃ annealed films. On the other hand, free electron density was suppressed well by the O₃ annealing even at low temperatures ≤ 200 °C. Moreover, even at 150 °C, the TFTs characteristics were improved to the subthreshold voltage swing of 217 mV/decade, the saturation mobility of ~ 11.4 cm²(Vs)^− 1 and the threshold voltage of 0.1 V by the O₃ annealing. It was also found that the effects of the O₃ annealing is more effective for thicker channel TFTs, which would be due to stronger oxidation power and the larger diffusion constant of oxygen atoms produced from O₃ molecules than those of O₂. These results substantiate that the O₃ annealing is more effective to improve TFT characteristics in particular for low-temperature processes at ≤ 200 °C.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

Zinc oxide thin film transistors using MgO-Bi1.5Zn1.0Nb1.5O7 composite gate insulator on glass substrate

We report on high mobility ZnO thin film transistors (TFTs) (< 5 V), utilizing a room temperature grown MgO-Bi_1.5Zn_1.0Nb_1.5O₇ (BZN) composite gate insulator on a glass substrate. 30 mol% MgO added BZN composite gate insulators exhibited greatly enhanced leakage current characteristics (~< 2 × 10^− 8 A/cm² at 0.3 MV/cm) due to the high breakdown strength of MgO, while retaining an appropriate high-k dielectric constant of 32. The ZnO-TFTs with MgO-BZN composite gate insulators showed a high field-effect mobility of 37.2 cm²/Vs, a reasonable on-off ratio of 1.54 × 10⁵, a subthreshold swing of 460 mV/dec, and a low threshold voltage of 1.7 V.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

Stability and high-frequency operation of amorphous In-Ga-Zn-O thin-film transistors with various passivation layers

The stability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) was investigated focusing on the effects of passivation layer materials (Y₂O₃, Al₂O₃, HfO₂, and SiO₂) and thermal annealing. Positive bias constant current stress (CCS), negative bias stress without light illumination (NBS), and negative bias light illumination stress (NBLS) were examined. It was found that Y₂O₃ was the best passivation layer material in this study in terms of all the stability tests if the channel was annealed prior to the passivation formation (post-deposition annealing) and the passivation layer was annealed at ≥ 250 °C (post-fabrication annealing). Post-fabrication thermal annealing of the Y₂O₃ passivation layer produced very stable TFTs against the CCS and NBS stresses and eliminated subgap photoresponse up to the photon energy of 2.9 eV. Even for NBLS with 2.7 eV photons, the threshold voltage shift is suppressed well to − 4.4 V after 3 h of test. These results provide the following information; (i) passivation removes the surface deep subgap defects in a-IGZO and eliminates the subgap photoresponse, but (ii) the bulk defects in a-IGZO should be removed prior to the passivation process. The Y₂O₃-passivated TFT is not only stable for these stress conditions, but is also compatible with high-frequency operation with the current gain cut-off frequency of 91 kHz, which is consistent with the static characteristics.     

Copper phthalocyanine thin-film field-effect transistor with SiO2/Ta2O5/SiO2 multilayer insulator

Top-contact Copper phthalocyanine (CuPc) thin-film field-effect transistor (TFT) with SiO₂/Ta₂O₅/SiO₂ (STS) multilayer as the dielectric was fabricated and investigated. With the multi-layer dielectric, drive voltage was remarkably reduced. A relatively large on-current of 1.1 × 10⁻⁷ A at a V_GS of −15 V was obtained due to the strong coupling capability provided by the STS multilayer gate insulator. The device shows a moderate performance: saturation mobility of μ_sat = 6.12 × 10⁻⁴ cm²/V s, on-current to off-current ratio of I_on/I_off = 1.1 × 10³, threshold voltage of V_TH = −3.2 V and sub-threshold swing SS = 1.6 V/dec. Atomic force microscope images show that the STS multilayer has a relative smooth surface. Experiment results indicate that STS multilayer is a promising insulator for the low drive voltage CuPc-based TFTs.     

Thin film transistors by solution-based indium gallium zinc oxide/carbon nanotubes blend

Solution-based indium gallium zinc oxide (IGZO)/single-walled carbon nanotubes (SWNTs) blend have been used to fabricate the channel of thin film transistors (TFTs). The electrical characteristics of the fabricated devices were examined. We found a low leakage current and a higher on/off currents ratio for TFT with SWNTs compared to solution-based TFTs made without SWNTs. The saturation field effect mobility (μ_sat) of about 0.22 cm²/Vs, the current on/off ratio is ~ 10⁵, the subthreshod swing is ~ 2.58 V/decade and the threshold voltage (V_th) is less than − 2.3 V. We demonstrated that the solution-based blend active layer provides the possibility of producing higher performance TFTs for low-cost large area electronic and flexible devices.     

Zinc cadmium oxide thin film transistors fabricated at room temperature

Zinc cadmium oxide (ZnCdO) transparent thin film transistors (TFTs) have been fabricated with a back-gate structure using highly p-type Si (001) substrate. For the active channel, 30 nm, 50 nm, and 100 nm thick ZnCdO thin films were grown by pulsed laser deposition. The ZnCdO thin films were wurtzite hexagonal structure with preferred growth along the (002) direction. All the samples were found to be highly transparent with an average transmission of about 80%~ in the visible range. We have investigated the change of the performance of ZnCdO TFTs as the thickness of the active layer is increased. The carrier concentration of ZnCdO thin films has been confirmed to be increased from 10¹⁶ to 10¹⁹ cm⁻³ as the film thickness increased from 30 to 100 nm. Base on this result, the ZnCdO TFTs show a thickness-dependent performance which is ascribed to the carrier concentration in the active layer. The ZnCdO TFT with 30 nm active layer showed good off-current characteristic of below ~ 10¹¹, threshold voltage of 4.69 V, a subthreshold swing of 4.2 V/decade, mobility of 0.17 cm²/V s, and on-to-off current ratios of 3.37 × 10⁴.     

High performance self-aligned top-gate ZnO thin film transistors using sputtered Al2O3 gate dielectric

High performance self-aligned top-gate zinc oxide (ZnO) thin film transistors (TFTs) utilizing high-k Al₂O₃ thin film as gate dielectric are developed in this paper. Good quality Al₂O₃ thin film was deposited by reactive DC magnetron sputtering technique using aluminum target in a mixed argon and oxygen ambient at room temperature. The resulting transistor exhibits a field effect mobility of 27 cm²/V s, a threshold voltage of − 0.5 V, a subthreshold swing of 0.12 V/decade and an on/off current ratio of 9 × 10⁶. The proposed top-gate ZnO TFTs in this paper can act as driving devices in the next generation flat panel displays.     

Enhancement-mode thin film transistor with nitrogen-doped ZnO channel layer deposited by laser molecular beam epitaxy

The thin film transistors (TFTs) based on nitrogen doped zinc oxide (ZnO) were investigated by laser molecular beam epitaxy. The increase of ZnO films' resistivity by nitrogen doping was found and applied in enhancement mode ZnO-TFTs. The ZnO-TFTs with a conventional bottom-gate structure were fabricated on thermally oxidized p-type silicon substrate. Electrical measurement has revealed that the devices operate as an n-channel enhancement mode and exhibit an on/off ratio of 10⁴. The threshold voltage is 5.15 V. The channel mobility on the order of 2.66 cm² V^− 1 s^− 1 has been determined.     

Ammonia-free chemically deposited CdS films as active layers in thin film transistors

In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12-0.16 cm²V⁻¹ s⁻¹ and 8.8-25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8-8.8 cm²V⁻¹ s⁻¹ and the threshold voltage decreased to 8.4-12 V. I_on/I_off for the annealed devices was approximately 10⁵-10⁶.