Over 1000 V/30 mA operation GaN-on-Si MOSFETs fabricated on Si substrates

We demonstrated the operation of GaN-on-Si metal-oxide-semiconductor field effect transistors (MOSFETs) for power electronics components. The interface states at SiO₂/GaN were successfully improved by annealing at 800 °C for 30 min in N₂ ambient. The interface state density was less than 1 × 10¹¹ cm^-2 eV⁻¹ at E_c − 0.4 eV. The n⁺ contact layers as the source and drain regions as well as the reduced surface field (RESURF) zone were formed using a Si ion implantation technique with the activation annealing at 1200 °C for 10 s in rapid thermal annealing (RTA). As a result, we achieved an over 1000 V and 30 mA operation on GaN-on-Si MOSFETs. The threshold voltage was +2.6 V. It was found that the breakdown voltage depended upon the RESURF length and nitride based epi-layer thickness. In addition, we discussed the comparison of each performance of GaN-on-Si with -sapphire devices.     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Effect of rapid thermal annealing on pentacene-based thin-film transistors

The bottom contact pentacene-based thin-film transistor is fabricated, and it is treated by rapid thermal annealing (RTA) with the annealed temperature up to 240 °C for 2 min in the vacuum of 1.3 × 10⁻² torr. The morphology and structure for the pentacene films of OTFTs were examined by scanning electron microscopy and X-ray diffraction technique. The thin-film phase and a very small fraction of single-crystal phase were found in the as-deposited pentacene films. While the annealing temperature increases to 60 °C, the pentacene molecular ordering was significantly improved though the grain size only slightly increased. The device annealed at temperature of 120 °C has optimal electrical properties, being consistent with the experimental results of XRD. The post-annealing treatment results in the enhancement of field-effect mobility in pentacene-based thin-film transistors. The field-effect mobility increases from 0.243 cm²/V s to 0.62 cm²/V s. Besides, the threshold voltage of device shifts from −7 V to −3.88 V and the on/off current ratio increases from 4.0 × 10³ to 8.7 × 10³.     

Au and non-Au based rare earth metal-silicide ohmic contacts to p-InGaAs

The aim of this study is to improve the electrical properties of ohmic contacts that plays crucial role on the performance of optoelectronic devices such as laser diodes (LDs), light emitting diodes (LEDs) and photodetectors (PDs). The conventional (Pd/Ir/Au, Ti/Pt/Au and Pt/Ti/Pt/Au), Au and non-Au based rare earth metal-silicide ohmic contacts (Gd/Si/Ti/Au, Gd/Si/Pt/Au and Gd/Si/Pt) to p-InGaAs were investigated and compared each other. To calculate the specific contact resistivities the Transmission Line Model (TLM) was used. Minimum specific contact resistivity of the conventional contacts was found as 0.111 × 10⁻⁶ Ω cm² for Pt/Ti/Pt/Au contact at 400 °C annealing temperature. For the rare earth metal-silicide ohmic contacts, the non-Au based Gd/Si/Pt has the minimum value of 4.410 × 10⁻⁶ Ω cm² at 300 °C annealing temperature. As a result, non-Au based Gd/Si/Pt contact shows the best ohmic contact behavior at a relatively low annealing temperature among the rare earth metal-silicide ohmic contacts. Although the Au based conventional ohmic contacts are thermally stable and have lower noise in electronic circuits, by using the non-Au based rare earth metal-silicide ohmic contacts may overcome the problems of Au-based ohmic contacts such as higher cost, poorer reliability, weaker thermal stability, and the device degradation due to relatively higher alloying temperatures. To the best of our knowledge, the Au and non-Au based rare earth metal-silicide (GdSi_x) ohmic contacts to p-InGaAs have been proposed for the first time.     

X-ray microdiffraction investigation of crystallinity and strain relaxation in Ge thin lines selectively grown on Si(0 0 1) substrates

We used X-ray microdiffraction (XRMD) to investigate the crystallinity and strain relaxation of Ge thin lines with widths of 100, 200, 500 and 1000 nm selectively grown on Si(0 0 1) substrates using a patterned SiO₂ mask by chemical vapor deposition. The variations of the strain relaxation in the line and width directions were also investigated in Ge thin lines with a width of 100 nm. After growth, crystal domains with very small tilt angles were detected in Ge lines with all four line widths. The tilt angle range was larger in thinner Ge lines. After annealing at 700 °C, the formation of a single, large domain with a specific tilt angle was detected by XRMD for Ge thin lines with widths of 100 and 200 nm. These experimental results reflect the effects of SiO₂ side walls around the Ge thin lines on crystallinity and strain relaxation of Ge.     

Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diode using low-temperature Si2H6 reaction for nanometer-order ultrathin Si barriers

Low-temperature Si barrier growth with atomically flat heterointerfaces was investigated in order to improve negative differential conductance (NDC) characteristics of high-Ge-fraction strained Si_1−xGe_x/Si hole resonant tunneling diode with nanometer-order thick strained Si_1−xGe_x and unstrained Si layers. Especially to suppress the roughness generation at heterointerfaces for higher Ge fraction, Si barriers were deposited using Si₂H₆ reaction at a lower temperature of 400 °C instead of SiH₄ reaction at 500 °C after the Si_0.42Ge_0.58 growth. NDC characteristics show that difference between peak and valley currents is effectively enhanced at 11-295 K by using Si₂H₆ at 400 °C, compared with that using SiH₄ at 500 °C. Non-thermal leakage current at lower temperatures below 100 K tends to increase with decrease of Si barrier thickness. Additionally, thermionic-emission dominant characteristics at higher temperatures above 100 K suggests a possibility that introduction of larger barrier height (i.e. larger band discontinuity) enhances the NDC at room temperature by suppression of thermionic-emission current.     

Formation of Ni(Ge1−xSnx) layers with solid-phase reaction in Ni/Ge1−xSnx/Ge systems

We have demonstrated the formation of Ni(Ge_1−ySn_y) layers on Ge_1−xSn_x layers by using solid-phase reaction for samples with Sn contents ranging from 2.0% to 6.5%. We have also investigated solid-phase reaction products in Ni/Ge_1−xSn_x/Ge samples after annealing and the crystalline properties of nickel-tin-germanide layer/Ge_1−xSn_x contact structures. After annealing at temperatures ranging from 350 to 550 °C, the formation of polycrystalline Ni(Ge_1−ySn_y) layers has been observed on epitaxial Ge_1−xSn_x layers with Sn contents ranging from 2.0% to 6.5%. We also observed anisotropic crystal deformation of NiGe with the incorporation of Sn atoms into substitutional sites in NiGe. In the case of the Ni/Ge_1−xSn_x/Ge sample with a Sn content of 3.6%, the formation of an epitaxial Ni₂(Ge_1−zSn_z) layer on the Ge_1−xSn_x layer was found. The formation of β-Sn crystallites was observed after annealing at above 450 °C in samples with a high Sn content of 6.5%. This β-Sn formation is due to the precipitation of Sn atoms. In all samples annealed at 350 °C, the morphology of Ni-Ge-Sn layers is smooth and uniform. However, the surface roughness and interface roughness increase for an annealing temperature of 550 °C. In particular, in the sample with a Sn content of 6.5%, the temperature at which agglomeration noticeably occurs is as low as 450 °C.     

Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10⁻¹¹ A, for the TFT without an offset region, to the low OFF current of 1.34 × 10⁻¹² A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10⁻⁶ S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.     

Growth of a Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition

We have made the successful growth of Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition (RTCVD). In order to overcome the large lattice mismatch between Ge and Si, we used a two-step growth method. Our method shows the uniformity of the thickness and good quality Ge layer with a homogeneous distribution of tensile strain and a lower etch pit density (EPD) in order of 10⁵ cm⁻². The surface morphology is very smooth and the root mean square (RMS) of the surface roughness was 0.27 nm. The photocurrent spectra were dominated by the Ge layer related transition that corresponding to the transitions of the Si and Ge. The roll-off in photocurrent spectra beyond 1600 nm is expected due to the decreased absorption of Ge.     

High-density formation of Ge quantum dots on SiO2

We formed high-density Ge quantum dots (QDs) on an ultrathin SiO₂ layer by controlling the early stages of low-pressure chemical vapor deposition (LPCVD) with a germane gas (GeH₄) assisted by a remote plasma of pure H₂. We then characterized the electronic charged states of the QDs by an AFM/Kelvin probe technique. The formation of single crystalline Ge-QDs with an areal dot density of ∼2.0 × 10¹¹ cm⁻² was confirmed after examining the surface morphology and lattice by atomic force microscopy and transmission electron microscopy, respectively. It has been suggested that an increase in the flux of deposition precursors due to efficient decomposition of GeH₄ by a supply of hydrogen radicals and the dehydration reaction of surface OH bonds plays a role in nucleation of Ge-QDs on SiO₂. Surface passivation with hydrogen may also promote the surface migration of deposition precursors during LPCVD. The surface potential of the dots changed in a stepwise manner with respect to the tip bias due to multistep electron injection into and extraction from the Ge-QDs.     

Subband structure and effective mass of relaxed and strained Ge (1 1 0) PMOSFETs

Effective mass and mobility of strained Ge (1 1 0) inversion layer in PMOSFET are studied theoretically in this paper. The strain condition considered in the calculations is the intrinsic strain resulting from growing the Ge layer on the (1 1 0) Si substrate. The quantum confinement effect resulting from the vertical effective electric field is incorporated into the k · p calculation. Various effective masses, such as quantization effective mass, m_z, density of states effective mass, m_DOS, and conductivity mass, m_C, as well as the hole mobility of strained Ge (1 1 0) inversion layer for PMOS under substrate strain and various effective electric field strengths are all investigated.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

Strained single-crystal GOI (Ge on Insulator) arrays by rapid-melting growth from Si (1 1 1) micro-seeds

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (1 1 1) micro-crystal seeds (∼1 μm?) is proposed. As a result, single-crystalline GOI (1 1 1) structures with large area (∼10 μm?) are realized. The transmission electron microscopy observations reveal no dislocation or stacking fault in the laterally grown regions. Moreover, the Raman measurements show that the tensile strain (∼0.2%) which enhances the carrier mobility is induced in the growth regions. This new method can be employed to realize the multi-functional SiGe large scale integrated circuits.     

Optimization of SiGe bandgap-based circuits for up to 300 °C operation

An investigation of the performance and reliability issues associated with operating silicon-germanium (SiGe) devices and circuits at temperatures up to 300 °C is presented, along with a new bypass compensation technique for optimizing bandgap reference performance at these extreme temperatures. In addition to the device-level characterization of a SiGe BiCMOS platform, improved circuit design and a device-level collector-substrate leakage suppression technique are shown to improve the viability of SiGe bandgap reference (BGR) circuits on low-cost, bulk Si wafers for high temperature applications. A shunting technique using various transistors to further improve BGR performance above 200 °C is presented, and optimized compensation designs predict new performance records for a bulk-silicon based technology across temperatures from −200 °C to 300 °C. Finally, a closely-related SiGe temperature sensor circuit is characterized for operating environments up to 300 °C.     

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications

This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV_p-p with a BER of 10⁻¹² at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV_p-p to 800 mV_p-p, indicating a BER of 10⁻¹². The chip core area is 0.3 × 0.3 mm² and it consumes 58 mW with a single supply voltage of 1.8 V.     

Study of Arsenic ion implantation of patterned strained Si NWs

A systematic study of the impact of As⁺ ion implantation on strain relaxation and dopant activation of biaxially strained SSOI layers and uniaxially strained/unstrained NWs is presented. Three aspects are investigated: (i) the quality of the single crystalline layers and the NWs, (ii) strain relaxation of the implanted NWs and (iii) dopant activation of the layers and NWs. Optimization of the doping conditions resulted into very low contact resistivities of NiSi contacts on strained and unstrained 70 nm SOI layers and Si NWs. For NW contacts values as low as 1.2 × 10⁻⁸ Ω cm² for an As⁺ dose of 2 × 10¹⁵ cm⁻² were achieved, which is 20 times lower than for planar contacts made under the same implantation and annealing conditions.     

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO₂/GeO₂ bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO₂-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O₂, to decrease oxygen content in the subsequent SiO₂ deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO₂ deposition, interface states density of 4 × 10¹¹ cm⁻² eV⁻¹ at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O₂, interface quality could be improved by an increase in oxygen contents during the subsequent SiO₂ deposition, but the interface quality was worse compared with BLP with O₂.     

High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI pFETs and SOI nFETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 °C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L = 160 nm). Excellent low-field mobility values for electrons in Si nFETs and holes in Ge pFETs were achieved (275 and 142 cm²/V/s resp.).     

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with high-quality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.08Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 106 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.08Ge0.2 layer. By employing P+ implantation and rapid thermal annealing,the strain relaxation degree of the Si0.08Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。