FPGA implementation and performance evaluation of a high throughput crypto coprocessor

This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).     

Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 × 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.     

单片机与FPGA/CPLD总线接口逻辑设计

设计一种基于MCS-51单片机与FPGA/CPLD的总线接口逻辑,实现单片机与可编程逻辑器件数据与控制信息的可靠通信,使可编程逻辑器件与单片机相结合,优势互补,组成灵活的、软硬件都可现场编程的控制系统.在设计中采用VHDL语言,实现MCS-51单片机与FPGA/CPLD的总线接口逻辑设计.试验表明,该总线接口逻辑工作稳定、可靠,使MCS-51单片机与FPGA/CPLD能够完美结合.     

Design,implementation, and evaluation of a single-copy protocol stack

Data copying and checksumming are the most expensive operations on hosts performing high-bandwidth network I/O over a high-speed network. Under some conditions, outboard buffering and checksumming can eliminate accesses to the data, thus making communication less expensive and faster. One of the scenarios in which outboard buffering and checksumming pays off is the common case of applications accessing the network using the Berkeley sockets interface and the Internet protocol stack. In this paper, we describe the host software for a host interface with outboard buffering and checksumming support. The platform used is DEC Alpha workstations with a Turbochannel I/O bus and running the DEC OSF/1 operating system. Our implementation does not only achieve ‘single copy’ communication for applications that use sockets, but it also interoperates efficiently with in-kernel applications and other network devices. Measurements show that for large reads and writes the single-copy path through the stack is five to seven times more efficient than the traditional implementation. We also present a detailed analysis of the measurements using a simple I/O model. © 1998 John Wiley & Sons, Ltd.     

一类基于事件/动作的传感器网络通讯协议设计与实现

本文针对工业过程中的现场监控设备特点,提出了一种轻量级的传感器网络协议.该协议在链路层中通过引入异步事件及主/从通信等模式,提高了实时事件响应性能;同时采用事件/动作模型,提供了一种独立于开发者和使用者、又具备扩展性的应用层协议.本文还给出了链路层协议的FPGA参考实现、应用层协议的参考实现及应用实例.     

基于.NET的特大型航空产品质量评估系统的设计与实现

产品复杂性的增加,对质量评估提出了更高的要求。针对特大型航空产品,综合现有的理论研究成果,提出了一种面向特大型航空产品的质量评估体系和模型。在此基础上,对特大型航空产品质量评估系统的流程和功能进行了设计。最后,对基于.NET的特大型航空产品的质量评估系统的实现技术和关键功能实现作了具体介绍。     

Design and implementation of a file system with on‐the‐fly data compression for GNU/Linux

Data compression techniques have long been assisting in making effective use of disk, network and other resources. Most compression utilities require explicit user action for compressing and decompressing of file data. However, there are some systems in which compression and decompression of file data is done transparently by the operating system. A compressed file requires fewer sectors for storage on the disk. Hence, incorporating data compression techniques into a file system gives the advantage of a larger effective disk space. At the same time, the additional time needed for compression and decompression of file data gets compensated for to a large extent by the time gained because of fewer disk accesses. In this paper we describe the design and implementation of a file system for the Linux kernel, with the feature of on‐the‐fly data compression and decompression in a fashion that is transparent to the user. We also present some experimental results which show that the performance of our file system is comparable to that of Ext2fs, the native file system for Linux. Copyright © 1999 John Wiley & Sons, Ltd.     

基于B/S结构的高职人才培养评价机制抽样系统设计与实现

完善高职人才培养评价机制是发展高职教育的有效手段,“点线面体”立体型高职人才培养评价机制是对高职人才培养模式的创新和探索。介绍了基于B/S结构的“点线面体”立体型高职人才培养评价机制抽样系统的设计与实现,阐述了随机选取学生进行考核的分层抽样功能模块,总结了系统的实际应用。     

Conceptualization,development and implementation of a web-based system for automatic evaluation of mathematical expressions

Assessment and feedback are important parts of the teaching and learning of mathematics; and in general, the process can benefit by the introduction of technology. MathDIP is a web-platform which provides automatic evaluation and feedback of each step of the solution of a math problem. The system incorporates a Computer Algebra System to perform the evaluation and a mathematical expression editor which allows the user to interact with the system using his/her own handwriting. This paper reports on the design, development and evaluation of the system. The usability results of its implementation on an Introductory University Mathematics course show good performance in design and functionality issues. Also, results show that in general, the students participating in the study have a high level of acceptance for the system and perceive that its use motivated and strengthened their learning of the specific math topics covered in the course.     

Design and evaluation of a multimedia storage server for mixed traffic

The relative simplicity of access to digital communications nowadays and the simultaneous increase in the available bandwidth are leading to the definition of new telematic services, mainly oriented towards multimedia applications and interactivity with the user. In the near future, a decisive role will be played in this scenario by the providers of interactive multimedia services of the on-demand type, which will guarantee the end user a high degree of flexibility, speed and efficiency. In this paper, some of the technical aspects regarding these service providers are dealt with, paying particular attention to the problems of storing information and managing service requests. More specifically, the paper presents and evaluates a new storage technique based on the use of disk array technology, which can manage both typical multimedia connections and traditional requests. The proposed architecture is based on the joint use of the partial dynamic declustering and the information dispersal algorithm, which are employed for the allocation and retrieval of the data stored on the disk array. We also define efficient strategies for request management in such a way as to meet the time constraints imposed by multimedia sessions and guarantee good response times for the rest of the traffic. The system proposed is then analyzed using a simulation approach.     

Design, implementation and validation of a Europe-wide pedagogical framework for e-Learning

Within the context of a Europe-wide project UNITE, a number of European partners set out to design, implement and validate a pedagogical framework (PF) for e- and m-Learning in secondary schools. The process of formulating and testing the PF was an evolutionary one that reflected the experiences and skills of the various European partners and secondary schools involved in the project. The framework involved pedagogies which underpin the teaching of subject matter in a number of European secondary schools as well as the ways in which learning is delivered and assessed. The PF represents an essential part of the e-Learning system conceptualization and development and offers sound concepts for the development of learning scenarios in order to enhance the learning experience of students in secondary schools. A five-component framework which, by means of its constituents, drives and guides the creation of e-Learning scenarios was designed and tested. It is composed of the pedagogical framework context, pedagogical approaches, assessment techniques, teacher education and national specifics and current pedagogical practices implemented in national curricula. A series of learning scenarios were created to test the PF in classrooms. A detailed exemplar of a scenario in practice is offered. An evaluation of the scenarios based on [Reeves, T. C., 1994. Evaluating what really matters in computer-based education. In M. Wild, D. Kirkpatrick (Eds.), Computer education: new perspectives (pp. 219–246). Perth, Australia: MASTEC] pedagogical dimensions revealed that UNITE is based on constructivist and cognitive foundations. With increased experience of the system the teachers’ implementation of the pedagogical framework developed into increased mastery in the school context. Teachers from the second validation phase became more confident in their application of the framework principles and evaluated more positively the outcomes. This helped them to become more aware of the opportunities offered by the framework in their secondary school teaching. In order to bring this about the supports for change were put into place at the levels of pedagogical design, administrative support and the provision of the required resources and appropriate continuing professional development. The project has sought to create this support structure to ensure maximal benefits of the system for teaching and learning. Such a pedagogical support PF has offered scope for both collaborative and autonomous learning which have brought about value-added teaching and learning effects in the Europe-wide network of schools.     

Evolutionary development: a model for the design,implementation, and evaluation of ICT for education programmes

The impact of information and communication technology (ICT) in primary and secondary education is still an open question. Following review of the available literature, we classify the causes of the lack of impact on students' attainment in four dimensions: (1) the design and implementation of ICT in educational settings; (2) the evaluation of its impact; (3) the scaling up of these kinds of innovations; and (4) the cost‐effectiveness of technology‐enhanced learning environments. Based on this evidence, we proposed the evolutionary development model (EDM), which aims to produce a cost‐effective and sustainable ICT for education (ICT4E) programme in three steps: efficacy, effectiveness, and efficiency. In each step, one component of the programme is built and validated in real educational settings. Therefore, the resultant ICT4E programme is ready to be replicated across the school system. We also show how the EDM guided the development of a programme based on mobile computer supported collaborative learning, known as Eduinnova. Finally, we discuss how EDM can serve as an analysis tool for researchers and policy makers.     

Design and implementation of a dual‐band concurrent fully‐integrated LNA for WLAN IEEE 802.11a/b/g applications

This article presents a dual‐band concurrent fully‐integrated low‐noise amplifier (LNA) targeted to WLAN IEEE 802.11a/b/g standards. The use of a concurrent topology enables saving die area and power consumption compared with the parallel solution that employs two separated LNAs. An original design methodology that helps in the selection of input/output matching network element values is also presented. The LNA die area is 1.0 × 0.9 mm² and it consumes 9 mW (5 mA at 1.8 V). © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.