A plug-and-play wideband RF circuit ESD protection methodology: T-diodes

A novel “plug-and-play” ESD protection methodology for wideband RF applications is demonstrated. This methodology, referred to as T-diodes, utilizes an integrated transformer together with classical ESD protection diodes. The T-diodes act as an artificial transmission line that, when placed as a “plug-and-play” ESD protection component in front of an unprotected wideband LNA, preserves the input matching of that LNA. As a demonstrator, a wideband RF LNA in 0.18 μm CMOS is protected above 4.5 kV HBM ESD robustness without degrading its bandwidth.     

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.     

Design methodology of a robust ESD protection circuit for STIprocess 256 Mb NAND flash memory

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n^- junction with n⁺ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

Internal chip ESD phenomena beyond the protection circuit

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects     

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

一种新型结构栅耦合ggNMOS ESD保护电路研究

针对现有栅耦合NMOS(gate coupled NMOS,gcNMOS)静电放电(electrostatic discharge,ESD)保护电路对特定ESD脉冲不能及时响应造成的“触发死区”现象,本文提出了一种全新结构的栅耦合栅接地NMOS(gate coupled gate grounded NMOS,gc-gg...     

RC-SCR: very-low-voltage ESD protection circuit in plain CMOS

A simple, novel RC-coupled very-low-voltage silicon controlled rectifier, electrostatic discharge protection circuit is reported, implemented in 0.35 μm CMOS, which is confirmed by transient electrostatic discharge simulation and measurement, and results in a very low triggering of 7 V, a 60% reduction over traditional silicon controlled rectifiers     

一种CMOS新型ESD保护电路设计

金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。     

A new on-chip ESD protection circuit with dual parasitic SCRstructures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies     

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.     

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

This paper reports an ESD internal gate-oxide damage occurred on the digital-analog interface of a mixed-mode CMOS IC. A new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces. Experimental verification has confirmed that the IC product can be rescued to pass 2-KV ESD stress from the digital/analog VDD to digital/analog VSS pads without causing any internal damage again.     

ESD circuit model based protection network optimisation for extended-voltage NMOS drivers

New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed. The models were experimentally validated in a standard 0.35 μm CMOS process which requires 20 V compatible structures. It is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions. A major application of this model is for initial ESD optimisation of complex mixed voltage analog circuits.     

An on-chip ESD protection circuit with low trigger voltage inBiCMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (~7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (~Ω). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (~80 V/μm width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips     

ESD failure analysis methodology

This paper reviews failure analysis methods and discusses the merits and pitfalls associated with some of the more common techniques as they relate to electrostatic discharge (ESD). Although advanced methods such as the focused ion beam will be discussed, the importance of more traditional methods such as liquid crystal, emission microscopy, passive voltage contrast and mechanical polishing will be emphasized. Case histories are based on ESD related failure analysis; however, many of the references cover general failure analysis methodology.     

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.     

一种抑制ESD保护电路闩锁效应的版图研究

针对具有低压触发特性的静电放电(electrostatic discharge,ESD)保护电路易闩锁的不足,本文结合CSMC0.6μm CMOS工艺,设计了一种可应用于ESD保护电路中的独立双阱隔离布局方案,这种方案不仅可以有效的阻断形成闩锁的CMOS器件固有纵向PNP与横向NPN晶体管的耦合,且兼容原有工艺而不增加版图面积。将此布局方案与常规保护环结构同时应用于笔者研制的具有低压快速触发特性双通路ESD保护电路中,通过流片及测试对比表明,该布局方案在不影响保护电路特性的同时,较常规保护环结构更为有效的克服了保护电路的闩锁效应,从而进一步提升了该保护电路的鲁棒性指标。本文的布局方案为次亚微米MOS ESD保护电路版图设计提供了一种新的参考依据。