未来的IC向垂直发展

几十年来,半导体制造商年复一年地缩小IC的晶体管尺寸,以达到摩尔定律所描述的不断增加的速度和性能,亦即约18个月芯片性能要翻一番.摩尔定律只有在电路的RC延时与信号传输延时相比可以忽略时成立.然而,对于亚微米来说,RC延时变为主要因素.曾经寄希望于改用铜金属化、低K介电质和化学机械抛光(CMP)来降低RC延时,以及缩小尺寸来达到由摩尔定律预期的未来十年的性能改进.     

Optimization for Chip Stack in 3-D Packaging

We have been developing three-dimensional (3-D) packaging technology for forming through-type electrodes in chips that are then directly connected in stacks. The model examined in this study is defined by its simple structure. The structure was optimized for successful connection in a chip stack without degrading the features of the chips. The use of this structure enabled a stable and rigid connection, and a four-layer chip stack assembled on a ceramic substrate exhibited adequate thermal cycle performance. This paper discusses how the structure of terminals was optimized for chip stacking. A finished package assembled from static random access memory (SRAM) with through-type electrodes was confirmed to operate well and exhibit normal functioning.     

Study of the Au/In Reaction for Transient Liquid-Phase Bonding and 3D Chip Stacking

The latest three-dimensional (3D) chip-stacking technology requires the repeated stacking of additional layers without remelting the joints that have been formed at lower levels of the stack. This can be achieved by transient liquid-phase (TLP) bonding whereby intermetallic joints can be formed at a lower temperature and withstand subsequent higher-temperature processes. In order to develop a robust low-temperature Au/In TLP bonding process during which all solder is transformed into intermetallic compounds, we studied the Au/In reaction at different temperatures. It was shown that the formation kinetics of intermetallic compounds is diffusion controlled, and that the activation energy of Au/In reaction is temperature dependent, being 0.46 eV and 0.23 eV for temperatures above and below 150°C, respectively. Moreover, a thin Ti layer between Au and In was found to be an effective diffusion barrier at low temperature, while it did not inhibit joint formation at elevated temperatures during flip-chip bonding. This allowed us to control the intermetallic formation during the distinct stages of the TLP bonding process. In addition, a minimal indium thickness of 0.5 μm is required in order to enable TLP bonding. Finally, Au/In TLP joints of ∅40 μm to 60 μm were successfully fabricated at 180°C with very small solder volume (1 μm thickness).     

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable behavior is essential for proper system operation. In CMPs, general-purpose processor cores are used to run software tasks of different applications and the communication between the cores cannot be precharacterized. Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task. In this paper, we address the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. In our synthesis approach, we use accurate delay and power models for the network components (switches and links) that are obtained from layouts of the components using industry standard tools. The synthesis approach utilizes the floorplan knowledge of the NoC to detect timing violations on the NoC links early in the design cycle. This leads to a faster design cycle and quicker design convergence across the high-level synthesis approach and the physical implementation of the design. We validate the design flow predictability of our proposed approach by performing a layout of the NoC synthesized for a 25-core CMP. Our approach maintains the regular and predictable structure of the NoC and is applicable in practice to existing NoC architectures.     

千兆赫超高速ADC新系统架构带来系统高性能

对电路设计者来说,开发千兆赫系统面临相当多的挑战——也就是在处理千兆赫模拟频率和千兆样品取样率时都要求具有非常精密的设计技术。这种系统的每个部分都需要通过精细的设计来达到最优化的性能,任何一个设计拙劣的模拟输入级或时钟驱动电路和不恰当的布线,都将导致动态性能上巨大的缩减,而要在每秒钟数百兆的频率下捕捉数据,更是个令人头痛的问题。要达到高速度、高性能放大器或ADO数据表的规格,需要具备多年的高速系统设计经验和精密的设计技术。     

3-D/2-D registration by integrating 2-D information in 3-D

In image-guided therapy, high-quality preoperative images serve for planning and simulation, and intraoperatively as "background", onto which models of surgical instruments or radiation beams are projected. The link between a preoperative image and intraoperative physical space of the patient is established by image-to-patient registration. In this paper, we present a novel 3-D/2-D registration method. First, a 3-D image is reconstructed from a few 2-D X-ray images and next, the preoperative 3-D image is brought into the best possible spatial correspondence with the reconstructed image by optimizing a similarity measure (SM). Because the quality of the reconstructed image is generally low, we introduce a novel SM, which is able to cope with low image quality as well as with different imaging modalities. The novel 3-D/2-D registration method has been evaluated and compared to the gradient-based method (GBM) using standardized evaluation methodology and publicly available 3-D computed tomography (CT), 3-D rotational X-ray (3DRX), and magnetic resonance (MR) and 2-D X-ray images of two spine phantoms, for which gold standard registrations were known. For each of the 3DRX, CT, or MR images and each set of X-ray images, 1600 registrations were performed from starting positions, defined as the mean target registration error (mTRE), randomly generated and uniformly distributed in the interval of 0-20 mm around the gold standard. The capture range was defined as the distance from gold standard for which the final TRE was less than 2 mm in at least 95% of all cases. In terms of success rate, as the function of initial misalignment and capture range the proposed method outperformed the GBM. TREs of the novel method and the GBM were approximately the same. For the registration of 3DRX and CT images to X-ray images as few as 2-3 X-ray views were sufficient to obtain approximately 0.4 mm TREs, 7-9 mm capture range, and 80%-90% of successful registrations. To obtain similar results for MR to X-ray registrations, an image, reconstructed from at least 11 X-ray images was required. Reconstructions from more than 11 images had no effect on the registration results.     

片上系统架构使便携式医疗设备设计更简单更低廉

众所周知,近年来便携式医疗电子已经有了极大的发展并且被广泛应用。越来越多的新产品已经在市场上出现。实效性好的可以大量生产的就是那些设计简单、性能优越的方案,这样才能保证设备成本降低。要做到这一点,设计师需要考虑功耗、成本、尺寸、器件的FDA认证,以及其他因素。     

为网络、通信和高端计算系统中的分布式供电架构选择芯片组

今天的许多系统,包括网络、通信开关、路由器和高端服务器都采用分布式供电架构(DPA)。本文概括了如何为每个功率级选择适当的整体架构和适当的芯片组。同时也讨论了器件技术和关键指标的平衡,以及这些因素如何影响功耗、相关的电效率和热性能。     

新型MP3解码芯片VS1001K及其应用

VS1001K是芬兰VLSISolution公司生产的新型MP3解码芯片。该芯片内含高质量的立体声数模转换器 (DAC)和耳机驱动电路 ,支持PCM数据输入。它还具有体积小、功耗低、接口简单、价格便宜等优点。文中介绍了VS1001K的引脚排列、内部结构和主要特点。同时重点介绍了VS1001K的SCI控制接口中各寄存器的功能和地址以及SDI数据接口的操作方法。最后给出了VS1001K的应用电路     

New wire interface for graded 3-D TLM

A new 3-D graded TLM model for thin radiating wires is presented. The model differs from previous TLM models because the wire is modelled at the interfaces between cells, rather than through the centre of the node. The connection between the TLM symmetrical condensed-node link lines and the line forms a 'wire interface'. The scattering algorithm for the interface and simulation results are given.<>     

第三代手机射频架构

大多数电信企业为获得3G许可证投入了巨额资金，现在他们还需要进行基础设施投资，以为这一企盼已久的技术提供支持。总的成本将会达数十亿英磅，因此电信商面临很大的压力，需要尽快偿还债务并快速获得赢利，达到这一目标的最快速的方法还是尽快启动3G的消费市场。对于价格竞争激烈的多媒体功能等服务，赢得消费者和商业客户青睐并迅速收回投资的关键是提供价格合理的手机。包括发射器和接收器在内的手机内部电路在手机成本中占了相当大的部分。为降低3G手机射频解决方案的总体成本，必须满足三个主要目标：即降低芯片成本、减少外部器件…     

Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec

Several parallel, pipelined and folded architectures with different throughput rates are presented for computation of DCT, one of the fundamental operations in image/video coding. This paper begins with a new decomposition algorithm for the 1-D DCT coefficient matrix. Then the 2-D DCT problem is converted into the corresponding 1-D counterpart through a regular index mapping technique. Afterward, depending on the trade-off between hardware complexity and speed performance, the derived decomposition algorithm is transformed into different parallel-pipelined and folded architectures that realize the butterfly operations and the post-processing operations. Compared to other DCT processor, our proposed parallel-pipelined architectures, without any intermediate transpose memory, have the features of modularity, regularity, locality, scalability, and pipelinability, with arithmetic hardware cost proportional to the logarithm of the transform length.     

新型收发信机的体系结构

本文主要以航空通信设备为例，概述了近年来接收机和发射机体系结构研究的进展情况以及拓扑结构。     

新一代网络运营商及其网络结构

一、光速经济呼唤CyberCarrier Internet商业化的成功,给传统通信网络带来了巨大的冲击,并且对人们的工作、学习及生活方式产生深刻的影响,形成了所谓的互联网经济.     

New and Improved Architectures for Montgomery Modular Multiplication

In this paper an improved Montgomery multiplier, based on modified four-to-two carry-save adders (CSAs) to reduce critical path delay, is presented. Instead of implementing four-to-two CSA using two levels of carry-save logic, authors propose a modified four-to-two CSA using only one level of carry-save logic taking advantage of pre-computed input values. Also, a new bit-sliced, unified and scalable Montgomery multiplier architecture, applicable for both RSA and ECC (Elliptic Curve Cryptography), is proposed. In the existing word-based scalable multiplier architectures, some processing elements (PEs) do not perform useful computation during the last pipeline cycle when the precision is not equal to an exact multiple of the word size, like in ECC. This intrinsic limitation requires a few extra clock cycles to operate on operand lengths which are not powers of 2. The proposed architecture eliminates the need for extra clock cycles by reconfiguring the design at bit-level and hence can operate on any operand length, limited only by memory and control constraints. It requires 2∼15% fewer clock cycles than the existing architectures for key lengths of interest in RSA and 11∼18% for binary fields and 10∼14% for prime fields in case of ECC. An FPGA implementation of the proposed architecture shows that it can perform 1,024-bit modular exponentiation in about 15 ms which is better than that by the existing multiplier architectures.

New Non-Volatile Memory Structures for FPGA Architectures

A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described. The PEs have small area, can be combined with components that use low operational voltage on the same CMOS logic process, are non-volatile, enable the use of fast thin-oxide pass transistors, and are reprogrammable. A novel non-volatile flip-flop for use within the logical elements is presented as well. In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.     

New approach to extract phase feature of 3-D objects by wavelength-scanning digital holography

Phaseinformationisoneofkeyfeaturesfor3Dob jectsespeciallyforalmosttransparentobject,suchas somebiologicaltissues.Thus,phasefeaturesaremost widelyappliedinrecognization,opticalmetrologyandsoon.Somemethodshavebeenproposedtoobtainthe phaseinformation[14]ofa3…     

A New Classification for Peer-to-peer Networks Architectures

The peer-to-peer networks can present not only characteristics from the peer-to-peer model, but also characteristics from the client-server model. Depending on the level of involvement of the nodes in these two models, the networks can be classified within a spectrum that varies from a more centralizing pole, to a more decentralizing one. This article presents a new classification of the various existing architectures of peer-to-peer networks, under the perspective of the level of centralization, aiming to provide a better understanding of the relationship of these two models, as well as the possibilities of implementation of peer-to-peer applications under different approaches.     

3G网络与WLAN的综合结构设计方案

本文回顾了多种3G和WLAN相结合的网络结构,在讨论了它们的性能后提出两种新的结构设计方案,即把UMTS网络分别通过节点SGSN和GGSN接入WLAN网络.介绍了利用OPNET对这两种网络结构进行仿真的方法,并进行性能分析和比较.