工作在动态阈值MOS的特性研究

通过将衬底和栅极连接在一起实现了MOSFET的动态阈值,DTMOS与标准的MOSFET相比具有更高的迁移率,在栅极电压升高时DTMOS阈值电压会随之降低,从而获得了比标准的MOSFET大的电流驱动能力。DTMOS是实现低电压、低功耗的一种有效手段。     

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.     

SOI 动态阈值MOS 研究进展

随着器件尺寸的不断缩小,传统MOS器件遇到工作电压和阈值电压难以等比例缩小的难题,以至于降低电路性能,而工作在低压低功耗领域的SOI DTMOS可以有效地解决这个问题。本文介绍了四种类型的SOI DTMOS器件．其中着重论述了栅体直接连接DTMOS、双栅DTMOS和栅体肖特基接触DTMOS的工作原理和性能．具体分析了优化器件性能的五种方案,探讨了SOI DTMOS存在的优势和不足。最后指出,具有出色性能的SOI DTMOS必将在未来的移动通讯和SOC等低压低功耗电路中占有一席之地。     

Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors

In this paper, low-frequency noise (LFN) in N- and P-channel dynamic-threshold (DT) MOSFETs on Unibond substrate (SOI) is thoroughly investigated and, especially, an improved formulation of classical McWhorter’s noise model is proposed. In order to confirm our approach, an experimental comparison between body tied and DTMOS on SOI substrate has been achieved in terms of LFN behaviour. Furthermore, two different types of DTMOS transistors have been used: with and without current limiter. The LFN in DTMOS is analysed in ohmic and saturation regimes and the impact of the use of a current limiter (clamping transistor) is thoroughly analysed. An explanation based on floating body effect inducing excess noise is also proposed.     

Ultra-Low voltage-power DTMOS based full-wave rectifier

In this paper, dynamic threshold MOS (DTMOS) transistor based full-wave rectifier with ultra-low power consumption is presented. The proposed circuit composed of only four NMOS and seven DTMOS transistors when many rectifier circuits consist of passive circuit components such as diodes, resistors and active circuit elements. The layout occupies an active area of 24.6 µm × 65.01 µm and post-layout simulation results performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. The rectifier circuit with ±0.2 V DC supply voltages can be operated up to approximately 500 MHz and consumes only 2.83 nW thanks to the DTMOS transistors.     

High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts

In this study, the characteristics of DT-pMOSFETs are discussed using the reverse Schottky substrate contacts. With this diode, the DTMOS can be operated at high voltage and temperature. In addition, it exhibited an improved driving current, DIBL, transconductance, and subthreshold slope. The driving current for DTMOS was 20% larger, and was 12 mV improved for DIBL under DTMOS operation. Furthermore, the NBTI effects of DTMOS were also reported for the first time. This is because DTMOS could operate just below 0.7 V of V_G due to the junction turn-on behavior. It is interesting to note that the shift of the ΔV_TH of pMOSFETs under NBTI measurement was significantly alleviated in the DT operating mode, about 30 mV improved after 10,000 s stressing, due to the alleviated electrical field across the gate oxide which was due to the substrate bias and the threshold voltage adjustment under DTMOS operation.     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

High-voltage and high-temperature applications of DTMOS with reverse Schottky barrier on substrate contacts

In this letter, for the first time, application of dynamic threshold voltage MOSFET (DTMOS) with reverse Schottky barrier on substrate contacts (RSBSCs) for high voltage and high temperature is presented. By this RSBSC, DTMOS can be operated at high voltage (>0.7 V), and exhibits excellent performance at high temperature in terms of ideal subthreshold slope, low threshold voltage and high driving current.     

Dynamic threshold pass-transistor logic for improved delay at lowerpower supply voltages

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation

In this paper, the influence of proton irradiation is experimentally studied in triple-gate Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS). The drain current, transconductance, Drain Induced Barrier Lowering (DIBL) and the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance and intrinsic voltage gain will be compared. Furthermore, the Low-Frequency (LF) noise will be also analyzed in the DT mode and the standard biasing configuration. The results indicate that the better electrical characteristics and analog performance of DTMOS FinFETs make them very competitive candidates for low-noise RF analog applications in a radiation environment.     

1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results

In this paper, we describe a novel low-voltage class-AB operational amplifier (opamp) based on dynamic threshold voltage MOS transistors (DTMOS). A DTMOS transistor is a device whose gate is tied to its bulk. DTMOS transistor pseudo-pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class-AB output. Two versions of the proposed opamp (opamp-A and opamp-B) were fabricated in a standard 0.18-mum CMOS process technology. Measurements under 5 pF and 10 kOmega load conditions gave, for opamp-A, a DC open-loop gain of 50.1 dB, and a unity gain bandwidth (GBW) of 26.2 MHz. A common-mode rejection ratio (CMRR) of 78 dB, and input and output swings of 0.7 V and 0.9 V, respectively, were achieved. Opamp-B has been optimized for biomedical applications, and is implemented to build the analog front-end part of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. A DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and input and output swings of 0.6 V and 0.8 V, respectively, were measured. Opamp-A consumes 550 muW with an input referred noise of 160 nV/radicHz at 1 kHz. Opamp-B consumes only 40 muW and exhibits a lower input referred noise of 107 nV/radicHz at 1 kHz     

1 V fully balanced differential amplifiers: Implementation and experimental results

We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

High-speed and energy-efficient subthreshold level converter for wider voltage conversion

Analog Integrated Circuits and Signal Processing - In this paper, a high speed and energy-efficient dynamic threshold MOSFET (DTMOS) based hybrid level converter (DTHLC) is proposed with wide...     

130nm PDSOI DTMOS体延迟研究

研究了基于IBM 8RF 130 nm工艺部分耗尽绝缘体上Si(PDSOI)动态阈值晶体管(DTMOS)体电阻、体电容以及体电阻和体电容乘积(体延迟)随Si膜厚度和器件宽度的变化.结果表明,Si膜厚度减小会导致体阻增大、体电容减小,但是体电阻和体电容的乘积却明显增大.Si膜厚度从200 nm减小到80nm,体延迟增加将近两个数量级.器件宽度增加使得体电阻和体电容都明显增大,DTMOS电路延迟也因此指数递增.推导出了PDSOI DTMOS的延迟模型,为SOI DTMOS器件设计提供了参考.     

A monolithic based NIRS front-end wireless sensor

This paper concerns a novel analog front-end of a wireless brain oxymeter smart sensoring instrument based on near-infrared spectroreflectometry (NIRS). The NIRS sensor makes use of dynamic threshold transistors (DTMOS) for low voltage (1 V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs use DTMOS devices for input common mode range enhancement. The OTA was fabricated in a standard 0.18 μm CMOS process technology. Measurements under a 5 pF capacitive load for the OTA gave a DC open loop gain of 67 dB, unity frequency gain bandwidth of 400 kHz, input and output swings of 0.58 and 0.7 V, a power consumption of 18 μW, and an input referred noise of 134 nV/√Hz at 1 kHz without any extra noise reduction techniques. The achieved features of the proposed oxymeter front-end will allow ultra low-light level measurements, high resolution and good temperature stability.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs.