自缓释镍源的横向诱导晶化多晶硅薄膜晶体管

以镍硅合金靶作为溅射源,采用磁控溅射方法制备了一种自缓释镍源. 控制合适的自缓释镍源的准备条件,以单一方向横向晶化条件对非晶硅薄膜进行再晶化,可以获得低残余镍含量、大晶粒、高薄膜质量的多晶硅. 以此多晶硅为有源层进行了薄膜晶体管研究. 制备的p型TFT器件具有良好的特性,可有效地减小漏电流,同时具有很好的均匀性和稳定性.     

自缓释镍源的横向诱导晶化多晶硅薄膜晶体管

以镍硅合金靶作为溅射源,采用磁控溅射方法制备了一种自缓释镍源.控制合适的自缓释镍源的准备条件,以单一方向横向晶化条件对非晶硅薄膜进行再晶化,可以获得低残余镍含量、大晶粒、高薄膜质量的多晶硅.以此多晶硅为有源层进行了薄膜晶体管研究.制备的p型TFT器件具有良好的特性,可有效地减小漏电流,同时具有很好的均匀性和稳定性.     

多晶硅薄膜的两步激光晶化技术

采用两步激光晶化技术获得了多晶硅薄膜，分析计算了激光晶化时薄膜中的温度分布及表面温度与激光功率密度的关系，利用计算结果并优化了激光晶化时的工艺参数，采用该技术制备了性能优良的顶栅多晶硅薄膜晶体管，测量了薄膜晶体管的转移特性与输入输出特性，从多晶硅薄膜的制备工艺上分析了提高薄膜晶体管性能的原因。     

微波退火法制备多晶硅薄膜的电学特性研究

为实现多晶硅薄膜晶体管有源矩阵液晶显示器的实用化与产业化 ,低温 (<6 0 0°C)、快速制备高质量多晶硅薄膜已成为研究热点。文中将微波加热技术应用于金属诱导 a- Si薄膜横向晶化工艺中 ,成功实现了低温快速制备多晶硅薄膜。通过薄膜电阻率的测试 ,分析了多晶硅薄膜的电学特性。     

微波退火法低温制备多晶硅薄膜晶体管

多晶硅薄膜晶体管以其独特的优点在液晶显示领域中有着重要位置。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（小于600℃）高质量多晶硅薄膜已成为研究热点,文章利用微波加热技术,采用非晶硅薄膜微波退火固相晶化法低温制备出多晶硅薄膜晶体管,研究了微波退火工艺对多晶硅薄膜晶体管电学性能的影响。     

最优化多晶硅薄膜制成的高性能薄膜晶体管

多晶硅材料制备薄膜逻辑电路和开关阵列器件具有较高的电子迁移率的优点。然而,目前大多数研究工作注重于制备温度在1000℃左右的多晶硅材料,这就难免薄膜的再结晶。最近,英国GEC研究有限公司的Meakin等人报导了采用低得多的温度制备多晶硅材料的方法,并等一次详细探讨了淀积条件,薄的形貌和薄膜晶体管(TFT)特性之间的相互关系。     

MIC薄膜多晶硅材料的动态镍吸除技术基本机理及其应用

首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术.     

MIC薄膜多晶硅材料的动态镍吸除技术基本机理及其应用

首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术.     

微波退火非晶硅薄膜低温晶化研究

多晶硅薄膜晶体管以及其独特的优点在液晶显示领域中起着重要的作用。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（＜600℃高质量多晶硅薄膜已成为研究热点。文章研究了一种低温制备多晶硅薄膜的新工艺;微波退火非晶硅薄膜固相晶化法,利用X射线衍射、拉曼光谱和扫描电镜分析了微波退火工艺对非晶硅薄膜固相晶化的影响,成功实现了低温制备多晶硅薄膜。     

有机介质层铟锌氧化物薄膜晶体管

利用直流磁控溅射方法在玻璃基板上室温制备非晶铟锌氧化物半导体薄膜,薄膜表面平整。采用旋涂法室温制备聚四乙烯苯酚有机介质层。以铟锌氧化物薄膜作为沟道层、聚四乙烯苯酚作为介质层,成功制备了顶栅结构的薄膜晶体管。测试结果表明,所制备的薄膜晶体管具有饱和特性且为耗尽工作模式,薄膜晶体管的阈值电压为3.8V,迁移率为25.4cm2.V-1.s-1,开关比为106。     

Electric field-enhanced metal-induced lateral crystallization and P-channel poly-Si TFTs fabricated by it

The poly-Si thin film was obtained by electric field-enhanced metal-induced lateral crystallization technique at low temperature. Raman spectra, X-ray diffraction (XRD) and scan electron microscope (SEM) were used to analyze the crystallization state, crystal structure and surface morphology of the poly-Si thin film. Results show that the poly-Si has good crystallinity, and the electric field has the effect of enhancing the crystallization when DC electric voltage is added to the film during annealing. Secondary ion mass spectroscopy (SIMS) shows that the metal Ni improves the crystallization by diffusing into the a-Si thin film, so the crystallization of the lateral diffused region of Ni is the best. The p-channel poly-Si thin film transistors (TFTs) were fabricated by this large-size grain technique. The I_DS−V_DS and the transfer characteristics of the TFTs were measured, from which, the hole mobility of TFTs was 65 cm²/V s, the on and off current ratio was 5×10⁶. It is a promising method to fabricate high-performance poly-Si TFTs at low temperature for applications in AMLCD and AMOLED.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Poly-Si Thin Film Grown by Excimer Laser Crystallization and Its Ellipsometric Analysis

A novel approach of two-step laser crystallization for the growth of poly-Si thin film on glass substrate is investigated. Using this approach, we fabricated poly-Si thin film transistors with electron mobility of 103 cm2/V·s and on/off current ratio of 1×10~7.They are better than those of the poly-Si TFTs fabricated by conventional single-step excimer laser crystallization. We also analyzed the structure of the laser crystallized poly-Si thin film by spectroscopic ellipsometry, and proposed the models to simulate the poly-Si thin film and calculated the ellipsometric spectra. The calculated results are in good agreement with the measured results.     

Fabrication of Poly—Si TFT by Al—induced Lateral Crystallization at Low Temperature

Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-gate metal oxide semiconductor (MOS) transistor is discussed using a device simulator. The simulation results predict that the nonself-aligned bottom-gate MOS transistor cannot be scaled into the deep submicron regions. A simple fully self-aligned bottom-gate (FSABG) metal oxide semiconductor field effect transistor (MOSFET) technology is then proposed and developed. A new technique for forming thermal oxide on poly-Si serving as the bottom-gate dielectric is also investigated. It is found that the quality of the oxide on the poly-Si recrystallized by the metal induced uni-lateral crystallization (MIUC) is much higher than that by the solid phase crystallization (SPC). Deep submicron fully self-aligned bottom-gate pMOS transistors are fabricated successfully using the proposed technology. The experimentally measured results indicate the device performances depend strongly on the channel-width, and get comparable to that of a single crystal MOSFET if the channel width is less than 0.5/spl mu/m. The effects of the channel width on the device performances are discussed. In addition, the experimental results also confirm that the proposed technology has a good control of the channel film thickness.     

Improving the Electrical Properties of NILC Poly-Si Films Using a Gettering Substrate

Ni-metal-induced lateral crystallization (NILC) of amorphous silicon (alpha-Si) has been employed to fabricate poly-crystalline silicon (poly-Si) thin-film transistors. However, current crystallization technology often leads to Ni and NiSi₂ precipitates being trapped, thus degrading the performance of the device. We proposed using alpha-Si-coated wafers as Ni-gettering substrates. After bonding the gettering substrate with the NILC poly-Si film, both the Ni-metal impurity within the NILC poly-Si film and the leakage current were greatly reduced, thus increasing the ON/OFF current ratio.     

A study on the leakage current of poly-Si TFTs fabricated by metal induced lateral crystallization

Leakage current of poly-Si TFT fabricated by a metal induced lateral crystallization(MILC) process was investigated in terms of metal contamination and crystallization mechanisms. MILC poly-Si TFTs showed a higher leakage current than those by the solid phase crystallization method at high drain voltages. It turned out that the Ni rich phases in the depleted junction region played the role of trapping and recombination centers to generate the leakage currents and that the leakage current was generated by thermionic field emission. The leakage current could be drastically reduced to 5 pA/μm at V_GS=0 V and V_DS=15 V after the exclusion of the Ni-rich phase from the junction region by a Ni offset MILC process.