磁控溅射法制备的MoO_x薄膜材料特性

MoO_x材料因其较低的反射率,在窄边框液晶显示技术等领域是一种理想的材料。本文利用磁控溅射法在玻璃基板上制备MoO_x薄膜,并在MoO_x薄膜上沉积不同的金属层,采用不同的方法研究MoO_x薄膜及其搭配金属层的特性。测试结果表明:MoO_x和玻璃基板的粘附性较好,无须打底膜可在玻璃基板上直接沉积;MoO_x和Al及Cu的粘附效果优于Mo及MTD等Mo合金;MoO_x薄膜的方块电阻值较大,搭配金属层时可忽略不计;MoO_x厚度对搭配金属膜的反射率及色差影响很大,而金属层厚度影响较小。对于采用MoO_x作低反材料的工艺,可以根据MoO_x材料的特性选择搭配不同的金属层,在满足反射率等要求的基础上,可通过调整MoO_x层厚度来调整产品的色差,以满足客户的颜色喜好需求。     

网状斑点不良分析研究

针对网状斑点(Emboss Mura)不良现象进行系统研究,确定不良发生的机理,并找到有效的改善措施。首先通过半导体参数测试设备和改变电压、频率等方法测试Mura电学特性,然后采用扫描电子显微镜、椭偏仪对栅极绝缘层进行测量,最后采用扫描电子显微镜、X射线电子能谱对玻璃基板背面Mura形貌和成分进行测试,对Mura产生的原因提出合理的解释,并给出有效的改善措施。结果表明,Emboss Mura是干刻反应腔下部电极的阵列凸起划伤玻璃基板背面和凸起碎屑粘附在划伤处形成的。通过更改电极凸起的形状、结构、材质以及下部电极清洁方式、优化电极温度、增加PI膜厚等方式可以极大降低不良的发生率。     

基于ANSYS液晶玻璃基板的应力分析

为了管控紫外光固化工艺过程掩膜版的裂纹,基于ANSYS对受石英棒吸附的液晶玻璃基板的结构应力及升降温过程的热应力进行仿真分析,讨论了不同材料和不同厚度玻璃基板的结构应力及热应力变化。结构应力分析结果表明,基板挠度、等效应力和弯曲应力最大值均出现在中部;基板厚度增加时,最大应力值显著减小。热应力分析结果表明,当玻璃基板存在温度梯度时,升温较大的区域,玻璃基板挠度更大;随着温度先增大后减小,玻璃基板挠度、等效应力与弯曲应力均先增大后减小,且升降温过程中基板应力变化显著,等效应力变化最大,弯曲压应力变化较小,弯曲拉应力变化最小。玻璃基板等效应力和弯曲拉应力最大值分别达到44.8 MPa和5.79 MPa。优化设备降温系统,降低玻璃基板各区域的温度梯度与基板升温值等可有效防止玻璃破裂的发生。     

L0周边Mura分析及其改善研究

L0周边Mura是TFT-LCD的一种常见缺陷。本文对L0周边Mura发生原因进行分析,发现真空对盒工艺进行过程中玻璃基板表面受力不均使力学合成力较少的局部位置发生形变并引起液晶屏周边区域盒厚波动,产生不良。采用辅助封框胶开环方式,主封框胶内外两侧压差趋于平衡,L0周边Mura发生率大幅降低;而通过优化辅助封框胶工艺有效地解决了周边区域力学失衡难题,不良发生率降至0.3%,改善效果明显。此外,周边优化设计方案有助于新产品开发阶段避免该不良发生。     

摩擦工艺不良的探究

TFT-LCD的摩擦工艺中,容易产生摩擦Mura、L0条形不均、摩擦划伤等不良。分析及验证发现:摩擦Mura的发生与摩擦强度较弱,聚酰亚胺膜配向力不足引起像素漏光相关。选择摩擦强度好的尼龙布,并控制摩擦布寿命在100张基板以下,可以有效控制不良的发生。通过工艺调整加强摩擦强度时需考虑Zara发生情况,选择摩擦Mura和Zara总体发生较低的摩擦强度是必要的。采用摩擦辊垂直基板短边设计,可一定程度控制摩擦Mura的发生;长条型像素设计可从源头防止漏光产生。产品设计时避免显示区延伸区域大块金属的干涉可一定程度防止条形不均发生,以信号层作为绑定IC引线较之开关层做引线对条形不均改善有更好的效果。棉布的棉籽剪裁、摩擦设备机台的及时有效清洁、基板来料的超声波清洗是防止摩擦划伤发生的有效保证。     

TFT-LCD重力Mura的影响因素

重力Mura不良一直是显示业内一种比较难以解决的顽疾。随着显示屏透过率及对比度的要求不断提高,产品设计安全范围变得更小,因此重力Mura不良的解决更是尤为关键。本文对显示屏内部特性因素进行了分析,并通过工艺变更样品制作,进行液晶量安全范围(LC Margin)实验测试。证明了引起LC Margin变化的主要因素为柱状隔垫物(PS)高度,同时阵列基板上的源极信号体(S/D)膜层厚度和栅极(Gate)膜层厚度同样对LC Margin产生一定影响;CF基板上BMOCBlue膜层厚度、玻璃厚度特性参数也会导致LC Margin发生变化;在成盒(Cell)制作工艺中,PI膜层厚度及液晶型号对LC Margin的产生影响虽然不大,但也不容忽视;通过这样的实验论证,为业内研究提供相关依据,也为企业提供验证经验,保证产品的品质。     

摩擦Mura机理和设计改善方法

摩擦Mura是ADS型TFT-LCD中一种常见不良,本文主要对摩擦过程中固定位置的Mura进行理论研究和实验测试。摩擦Mura产生原因是TFT基板上的源极线附近的摩擦弱区漏光。从产品设计方面找出影响这种固定位置的摩擦Mura的主要因子为ITO材质、段差、过孔密度。ITO材质为金属材质,摩擦时对摩擦布损伤较大,摩擦方向上ITO越长对摩擦布损伤越大,摩擦Mura越明显。设计时需要尽力保证摩擦方向上ITO长度一致。段差会导致摩擦布经过高低不同区域时产生损伤,设计时需要尽力保证摩擦方向上段差一致。过孔是密度影响,孔径直径(5μm)摩擦布毛直径(11μm),密度越小则摩擦Mura越轻。以15.0FHD产品为例,对周边电路设计位置ITO材质/源极线/过孔密度等膜层进行设计优化,摩擦Mura发生率从5%降至0%,改善效果明显。     

关于TN型TFT-LCD中周边Mura的分析与改善

周边Mura在TN型TFT-LCD(Thin film transistor-liquid crystal display)生产中较为常见的一种不良,对画面品质影响较大,文章结合实际生产情况对周边Mura发生的原因进行理论分析和实验验证,周边Mura为光学性不良,通过调整Rubbing强度或者是增加Rubbing Cloth的恢复力等手法验证改善。最终实验得出在实际生产过程中调整Rubbing Cloth厚度和Aging时间,不良率降低80%以上,提高了产品品质。     

未确认Mura分析及改善对策

未确认Mura是一种能够影响TFT-LCD画面品质的不良。文章对未确认Mura不良进行了详细的分析,认为扇形区域出现有源层残留是导致未确认Mura不良发生的原因,介绍了一种通过变更曝光工艺条件来解决此种不良的方法,并通过试验论证了此方法的量产可行性。     

高储能密度玻璃-陶瓷电容器内电极的研究

采用Na2O-PbO-Nb2O5-SiO2体系玻璃-陶瓷作为绝缘介质,以磁控溅射镀膜技术先在玻璃-陶瓷层表面形成金属膜,再用丝网印刷技术在金属膜上涂覆银浆形成组合式内电极,制备出多层结构高储能密度玻璃-陶瓷电容器,对比了单层内电极结构电容器的性能参数。结果表明:多层内电极结构既保证电容器电极面积不会因银浆烧结形成微孔而减小,又能从原理上有效提高电容元件的击穿强度,其储能密度提高到约8 J/cm3。     

TFT-LCD制造工艺中金属或金属复合膜层坡度角的研究

在薄膜晶体管液晶显示器(TFT-LCD)面板制程中,Gate层(栅极)电路和SD层(源极)电路根据产品电阻等要求可以使用纯金属膜层,如钼、铜等金属膜层,也可以使用金属复合膜层,如铝钼、铝钕钼、钼铝钼等金属复合膜层。当使用不同金属或金属复合膜层作为Gate、SD电路时,应当对应不同的刻蚀液。但在实际生产时,往往是一种刻蚀液同时对应金属膜层或金属复合膜层。由于钼金属膜层的Etch Rate(刻蚀速率)大于铝钼等金属复合膜层Etch Rate,所以当铝钼等金属复合膜层刻蚀完成后对应坡度角有时会存在异常,如膜层角度较大(80～90°)、顶层金属钼发生尖角或缩进等现象,产生宏观不良及进行后工序时会产生相应的光学不良或导致后层物质残留,影响产品品质。本文针对金属膜层或金属复合膜层坡度角进行影响因素分析,主要受刻蚀工序及曝光工序影响。通过对刻蚀液浓度调整、温度调整、刻蚀方式调整及曝光工序等调整减少金属钼发生尖角、缩进几率,将金属膜层坡度角控制在60°左右及金属复合膜层坡度角控制在50°左右,从而降低不良的发生率,提高产品品质。     

TFT-LCD制造工艺中金属残留的解决方案

在TFT-LCD阵列的四次掩模技术中,复合层刻蚀是非常难控制的一道工序,最突出的问题是在复合层刻蚀后信号线的两边有金属残留,金属残留会对之后的绝缘层产生影响,导致断层等不良.调整复合层刻蚀工艺是目前解决金属残留问题的通用方法,但是都没有根本地解决这个问题.文章通过研究信号线刻蚀时间对复合层刻蚀后金属残留的影响,认为通过...     

TFT-LCD阵列腐蚀性缺陷分析(英文)

在TFT-LCD的生产过程中,阵列金属被腐蚀是造成TFT-LCD产品缺陷(亮线、薄亮线等)的常见原因。文章对实际生产过程中阵列基板的一种典型腐蚀性缺陷,应用扫描电子显微镜(SEM)、聚焦离子束(FIB)和能谱仪(EDS)等工具,并且结合BO(Business Objects)、CIM(Computer Integrated Manufacturing)等数据统计软件进行了分析。确定了造成缺陷的原因是栅金属暴露在含氯元素的酸性气体中被腐蚀,还确定了酸性气体的泄露源,并且推断出其形成机理:腐蚀发生在栅金属刻蚀(Gate Etch)工艺和多层膜沉积(Multi-Deposition)工艺之间,随后的多层膜沉积工艺的抽真空过程促进了缺陷的进一步形成。另外,针对发生此种缺陷时的应急措施进行了探讨。     

Excimer Laser Projection Photoablation Patterning of Metal Thin Films for Fabrication of Microelectronic Devices and Displays

A nonlithographic process is demonstrated for patterning Al, Cr, Cu, Ni, Ti, and W thin films, which are widely used in microelectronic and display fabrication. A projection photoablation process using 248-nm-deep ultraviolet radiation from a KrF excimer laser was used to pattern a polyimide film coated on a SiN layer deposited on glass. The photoablation-patterned polyimide film was used as a sacrificial layer in a lift-off patterning process for the metal films, which resulted in clean metal patterns with fine line-edge definition being fabricated after lift-off. This process provides a simpler and more economical patterning technique compared to conventional lithography methods, eliminating the developing and etching steps.     

低翘曲度ITO透明导电膜玻璃的工艺研究

研究了不同厚度ITO膜的大尺寸超薄导电玻璃的翘曲度,ITO膜形成期间基片温度对ITO膜层晶体化程度的影响及不同基片温度下形成的ITO膜层在不同的退火条件下的退火前、后的电阻率和膜压应力.实验发现,ITO膜层的很高的压应力是导致导电膜玻璃翘曲的直接原因;采用室温沉积非晶ITO膜,然后经高温热退火可获得低膜压应力多晶相ITO膜.基于实验结论,提出了一种适合批量生产的低翘曲度ITO膜导电玻璃的制备工艺.     

Active circuits under wire bonding I/O pads in 0.13 μmeight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology

Active circuits in terms of ring oscillator are moved to the place under the wire bonding pads in 0.13 μm full eight-level copper metal complementary metal-oxide-semiconductor process with fluorinated silicate glass low-k inter-metal dielectric. The bond pad with the 12 kÅ thick aluminum metal film as a bonding mechanical stress buffer layer is deposited on the topmost copper metal layer. No noticeable degradations in gate delay or cycle time of ring oscillator are detected in a variety of test structures subjected to bonding mechanical stress and thermal cycling stress. This indicates that the underlying process technology may be reliable and manufacturable in placing active circuits under the bonding pads and thereby the die area utility is recovered fully. More evidence is created from transmission line pulsing experiments as well as capacitive-coupling experiments     

A thin-film integrated incandescent display

Incandescent alphanumeric displays using a 16-bar format are obtainable today. They employ 1-ml incandescent tungsten helices strung between support posts. This paper describes a new incandescent display device, fabricated by microelectronic thin-film techniques. Such techniques allow high-resolution dot-matrix displays to be produced with all the cost advantages obtained from the employment of modern LSI thin-film processing. The device uses a ceramic substrate covered with a thick layer of glass. Holes are produced in the laminate and filled with metal to eventually form the element support posts. A thin layer of refractory metal is deposited on the glass. The metal and glass are then etched to produce a field of free-standing microfilaments. The resulting display panel can be driven by simple integrated circuits, and the efficiency of the device, operating at 1200°C, is better than quoted for most light-emitting diodes (LED's).     

Electronic properties of Cu(In,Ga)Se2 solar cells on stainless steel foils without diffusion barrier

Compared with rigid glass, manufacturing of Cu(In,Ga)Se₂ (CIGS) solar cells on flexible stainless steel (SS) substrates has potential to reduce production cost because of the application of roll‐to‐roll processing. Up to now, high‐efficiency cells on SS could only be achieved when the substrate is coated with a barrier layer (e.g. SiO_x or Si₃N₄) for hindering the diffusion of impurities, especially Fe, into the CIGS layer. In this paper, the effect of these impurities on the electronic transport properties of the device is investigated. Using admittance spectroscopy, the presence of a deep defect level at around 320 meV is observed, which deteriorates the efficiency of the solar cells. Furthermore, it is shown that reducing substrate temperature during CIGS deposition is an effective alternative to a barrier layer for reducing diffusion of detrimental Fe impurities into the absorber layer. By applying a CIGS growth process for deposition at low substrate temperatures, an efficiency of 17.7%, certified by Fraunhofer Institute ISE, Freiburg, was achieved on Mo/Ti‐coated SS substrate without an additional metal‐oxide or metal‐nitride impurity diffusion barrier layer. Copyright © 2012 John Wiley & Sons, Ltd.     

Dependence of the Fracture of PowerTrench MOSFET Device on Its Topography in Cu Bonding Process

Dependence of the fracture-resistance of a PowerTrench MOSFET device on its topography in Cu bonding process was investigated. Two different topographies, namely dimple and round, have been tested. A significantly higher cratering rate has been clearly observed on dimple topography. The dimple topography exhibited a cratering rate of 371 k ppm levels compared to 0 ppm in round topographies. Three-dimensional nonlinear finite-element analysis has shown that the largest compressive and shear stresses and their locations were identified, respectively, in borophosphosilicate glass (BPSG)/barrier metal layers of the dimple topography. The round topography had the smallest stress in BPSG/barrier metal layers. The higher compressive stress transferred to silicon in the dimple topography during the bonding process can induce a local crack, consequently causing silicon fracturing during the shearing processes. A significant improvement in the cratering performance was observed when the Al bond pad metal layer was reinforced by adding a barrier layer sandwiched in the Al metal layers. The cratering rate decreased to 1300 ppm levels. Additionally, the change in composition of a BPSG layer caused cratering was briefly discussed and an oxygen rich BPSG film in round topography was confirmed by the energy dispersive spectroscopy (EDS) of a cross-sectional TEM sample. It has been found that the cratering rate on dimple topography significantly increased from 1 k ppm to 100 k ppm levels, when the resulting residual Al pad thickness is less than 0.65 $mu$m for Cu bonding performed with different ultrasonic (US) power and bond forces.      

High-reliability tungsten-stacked via process with fully convertedTiAl3 formation annealing

The tungsten-stacked via structure will be widely used in future generations of semiconductors to increase the density of aluminum wiring. One problem with this structure is that film separation is sometimes observed at the interface between the aluminum wiring and the oxide layer. This separation occurs only in the specific stacked via structure, and it carries a risk of a potential reliability of via open problem. Some experiments aimed at solving this separation problem revealed that the stress induced by insufficient TiAl₃ formation during the heat cycle of metal annealing is strongly related to the film separation. The occurrence of the insufficient TiAl₃ formation is highly dependent on the condition of the interface between the titanium and aluminum, and it is also dependent on the ambient gas used for the ramp-up step in the metal annealing process. If these processes are optimized properly the stress value of TiAl₃ formation indicates the position of the maximum stress point during metal annealing. It was demonstrated that monitoring of the maximum stress point is one method for determining whether the TiAl₃ is fully formed