Optical computing advances logically for image processing

A powerful application of optical computation, digital optical cellular image processing (DOCIP), is discussed. DOCIP uses digital optical computing techniques to perform cellular logic operations or extended array functions on images. Cellular logic is reviewed, and a binary image algebra (BlA) that serves as an analysis and synthesis tool for cellular image processing systems is described. Some DOCIP architectures that have been proposed or experimentally demonstrated are discussed and classified as image-algebra-type processors or symbolic-substitution-type processors. The optical and optoelectronic implementations of these architectures are also discussed     

Experimental evaluation of the 3-D optical shuffle interconnectionmodule of the sliding Banyan architecture

A free-space optical interconnection module for the sliding Banyan (SB) multistage interconnection network is experimentally evaluated. This three-dimensional (3-D) optical shuffle topology employs a macro-lens array in a reflective architecture. Interconnections for multiple stages are interleaved across a single two-dimensional (2-D) multichip array of “smart pixels”. The experimental module implements five interleaved stages of shuffle interconnections with approximately 10 μm resolution and 10 μm registration accuracy across a 10×10 cm, 256 node, simulated optoelectronic (OE) backplane. The experiments demonstrate the use of conventional refractive optical elements to implement the required shuffle interconnection pattern in a SB network. The results suggest that this reflective 3-D shuffle interconnected SB approach may lead to ATM switching fabrics with aggregate throughputs scaleable to >1 Tb/s. Such a system could be implemented with vertical cavity surface emitting laser (VCSEL) based smart pixel OE technology     

Optical fiber interconnection for the scalable parallel computingsystem

In this paper, we discuss the optical fiber interconnection technologies applied in the two types of parallel processing systems: 1) a backplane interconnection in a parallel processor array system and 2) a computing cluster network. We have set up a parallel processor array system using optical fiber to make point-to-point interconnection between processor elements and are developing a low-cost virtual parallel optical fiber interconnection link (VPOFLink) complying with peripheral component interconnect (PCI) local bus specifications for the computing cluster. VPOFLink is integrated with the popular PCI bus interface in order to make the link hold the same bandwidth as that of the PCI bus. It was fabricated as an available peripheral device that can been inserted into the bus slots of commercial computers directly and can operate under the control of PCI bus. Also in this paper, we demonstrate the optical fiber link for a ring network and the architecture of the ring network     

Design of a free-space 3-D crossover optical network

A new method is proposed to map an 2-D crossover network into an 3-D spatial structure. It makes use of an 2 × 4 micro-blazed grating array to realize vertical connections and horizontal connections, and provides straight connections using a mirror. A module of the 3-D crossover network integrating a polarizing beam-splitter, half-wave plate, micro-blazed grating array, half silvered mirror, spatial light modulator and mirror, will accomplish the functions of optical signal switching, multicast, and broadcast. The characteristics of this module are switching-transparency, high-speed performance, and easy-integration. It has been proved that this module can be implemented in free spatial optical interconnections and parallel computing systems.     

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.     

Performances of lightwave interconnection using spatial addressing(LISA) and its application for multi-processor systems

A novel architecture for free-space optical interconnections is described. Named lightwave interconnections using spatial addressing (LISA), it is comprised of optical array devices and simple electrical logic circuits. One application of LISA, an interconnection bus for multiprocessor systems, is proposed and discussed. The theoretical estimation of LISA's fan-out characteristics concludes that fan-out is limited by the characteristics of signal transmission rather than those of the optical system and the limitation is far higher than imposed by electrical interconnection. A 1×16 LISA was implemented and fundamental operations at 200 Mb/s are demonstrated     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

Reliable and fast reconfigurable hierarchical interconnectionnetworks for linear WSI arrays

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Θ(log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated     

A three-dimensional high-throughput architecture usingthrough-wafer optical interconnect

This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images. The vertical optical interconnections are realized using. Integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits. The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry. These silicon circuits are post processed to integrate the thin film optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and renting schemes. The performance of this network is comparable to that of a three-dimensional mesh. The processing architecture has been defined to minimize overhead for basic parallel operations. The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications     

Photorefractive optics in dynamic interconnection

Describes various techniques to implement optical dynamic interconnections using the photorefractive effect. Two categories of optical dynamic interconnections are discussed. One is based on free-space optics and the other on guided optics. These include a real-time volume hologram, a mutually pumped phase conjugator, a spatial light modulator, a waveguide, and a spatial soliton     

Optoelectronic integrated systems based on free-space interconnectswith an arbitrary degree of space variance

It is appealing to contemplate how VLSI or wafer-scale integrated systems incorporating free-space optical interconnection might outperform purely electrically interconnected systems. This paper first provides a uniform treatment of a general class of optical interconnects based on a Fourier-plane imaging system with an array of sources in the object plane and an array of receptors in the image plane. Sources correspond to data outputs of processing “cells,” and receptors to their data inputs. A general abstract optical imaging model, capable of representing a large class of real systems, is analyzed to yield constructive upper bounds on system volume that are comparable to those arising from “3-D VLSI” computational models. These bounds, coupled with technologically derived constraints, form the heart of a design methodology for optoelectronic systems that uses electronic and optical elements each to their greatest advantage, and exploits the available spatial volume and power in the most efficient way. Many of these concepts are embodied in a demonstration project that seeks to implement a bit-serial, multiprocessing system with a radix-2 butterfly topology, and incorporates various new technology developments     

Architecture of an all-optical circuit-switched multistageinterconnection network

An architecture of an all-optical multistage interconnection network is proposed. The network supports a circuit-switching model of communication and can provide parallel optical paths among input and output ports. It uses an address-based routing algorithm for path setup which, due to its decentralized nature, makes this network suitable for designing high-speed switching systems. These switches are commonly used in telephony and multiprocessor systems. The proposed architecture uses bistable optical devices, such as interference filters, as essential components of its switching modules. Since these devices can be easily fabricated, the implementation of this architecture is feasible. Various design issues related to optical clock generation, its distribution, data synchronization, and intensity restoration are also discussed     

Architectural framework for optical frequency division multiplexingsystems based on regular space-frequency interconnections

The paper describes a multistage interconnection network (MIN) with regular interconnections in three dimensions (two space dimensions and the third dimension is the frequency) and dimension-dependent switches. (Regular interconnections mean that the same interconnection principles are applied throughout the stages of the MIN.) The frequency domain is organized by introducing artificial dimensions. The architecture is interpreted as an optical frequency division multiplexing (OFDM) system with multidimensional interconnections and switches where the dimension is an additional design parameter. The multidimensional interconnections may be implemented using a combination of space and frequency channels. The frequency interconnections (data movements between channels) are expressed by the Kronecker product (KP) of permutation matrices. In this case the number of frequency conversion (FC) operations and the number of frequency channels crossed during the generation of interconnections and switching decreases. The architectural principles presented are of general interest for the study of transmission and processing in arbitrary large scale interconnection systems implemented in the 3-D physical space     

Trinary registers and counters using savart plate and spatial light modulator for optical computation in multivalued logic

Registers and counters are the most important devices in any system of computations. In this paper we have communicated the trinary registers and counters in modified trinary number （MTN） system. It is suitable for the optical computing and other applications in multivalued logic system. Here the savart plate and spatial light modulator （SLM） based optoelectronic circuits have been used to exploit the optical tree architecture （OTA） in optical interconnection network.     

A prototype 3D optically interconnected neural network

We report the implementation of a prototype three-dimensional (3D) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow compact, purely on-chip electronic H-tree type fan-in structure. The small prototype system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off system and was shown to distinguish any vertical line from any horizontal one in an image of 4×4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to 10⁴/cm² seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation     

虚焦点成像实现平行光输入的PS光互连

用平行光输入２Ｎ×２Ｎ 元素阵列,采用２×２ 全息透镜阵列的虚焦点成像方式,实现了元素阵列的ＰＳ（ＰｅｒｆｅｃｔＳｈｕｆｆｌｅ,即全混洗）光互连;透镜阵列直接实现ＰＳ光互连时,成像放大率为２Ｎ,成像距离ｌＨ 与Ｎ 成线性;当在全息透镜阵列后另引入一成像透镜Ｌ时,推导的成像距离公式和系统放大率公式表明：互连的成像距离主要与成像透镜焦距有关,成像放大率主要与成像透镜焦距和全息透镜焦距之比有关。相应的实验证明了各公式的正确性。     

Multistage shuffle networks with shortest path and deflectionrouting for high-performance ATM switching: the closed-loop shuffleout

A new class of switching architectures for broadband packet networks, called shuffleout, is described and analyzed. Shuffleout is basically an output-queued architecture with a multistage interconnection network built out of unbuffered b×2b switching elements. Its structure is such that the number of cells that can be concurrently switched from the inlets to each output queue equals the number of stages in the interconnection network. The switching element operates the cell self-routing adopting a shortest path algorithm which, in case of conflict for interstage links, is coupled with deflection routing. The basic version of this architecture is called open-loop shuffleout. This paper describes the closed-loop shuffleout architecture with 2×4 switching elements in which cells that have crossed the whole interconnection network re-enter the network as long as they are not successfully routed to the addressed switch outlet. This result is accomplished by adding to the basic open-loop structure recirculation paths so that each packet can cross several times the interconnection network. Two different solutions are proposed to implement such functionality, the buffered closed-loop shuffleout and the expanded closed-loop shuffleout architecture. Both these solutions aim at reducing the number of stages in the network, compared to the open-loop structure, so as to reduce the complexity of the switch internal wiring and to simplify the output queue interface     

Fully differential optical interconnections for high-speed digitalsystems

This work presents the design details and experimental results for a parallel optical link. The link is designed for connections within high-speed digital systems, specifically for board- and backplane-level interconnections. The link can contain as many fibers in parallel as technology permits. The unusual aspects of this interconnection system are that it is DC-coupled and uses fully differential inputs, two optical channels per signal, to achieve self-thresholding and noise immunity. A chip set consisting of a 2.5-Gb/s bipolar differential laser driver, a 800-Mb/s GaAs MSM (metal-semiconductor-metal) preamplifier array, a 800-Mb/s GaAs MSM preamplifier-postamplifier array, and a GaAs MSM preamplifier array in which each preamplifier has a different bandwidth varying from 300 Mb/s to 2 Gb/s has been designed, fabricated, and tested to serve as a vehicle for verifying the concept. Although the experimental testing of the entire interconnect system is not yet complete, the experimental studies presented show a bandwidth in excess of 800 MHz and excellent signal isolation between channels     

Spatial optical beam-forming network for receiving-mode multibeamarray antenna - proposal and experiment

This paper proposes an array antenna for multibeam reception with a beam-forming network (BFN) that uses spatial optical signal processing and also presents experimental results. In this antenna, signals received at individual antenna elements are converted to optical signals, and are optically divided from the directions of signal arrival by means of optical spatial Fourier transformation, and then the optical signals are reconverted into microwave signals at the BFN. In this BFN, to maintain optical path-length conditions, an optical integrated circuit is employed. We have experimentally investigated the optical signal processing performances of the BFN for multibeam reception. The experimental results show that optical beam direction is changed according to the signal arrival direction of an array antenna. Two multiple RF signals with different phase distributions are separated. The sidelobe level of the optical signal is reduced when amplitude distributions of optical signals are Chebyshev distributions. We also present the signal transmission behavior of this BFN. The measured carrier-to-noise-ratio degradation of this BFN is 2 dB at BER=10^-6 when 118.125-Mb/s QPSK modulated signal is input into the BFN     

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.