一种高速JPEG2000 MQ编码器的VLSI实现

JPEG2000采用的MQ编码器是一种优于Huffman编码的无损数据压缩算法。基于JPEG2000算法规程的MQ编码器速度较慢,限制了整个编码系统的实时性。本文采用部分并行算法,MQ编码器每个时钟最多可以编码2对数据,有效提高了编码器的数据吞吐率,并设计了基于3级流水的VLSI结构。试验结果表明,该算法平均每个时钟编码1.32bit,比普通算法的编码效率提高了约32%。     

一种适用于JPEG2000的流水线MQ编码器设计

JPEG2000采用基于上下文的MQ算术编码来增强压缩效果,但其实现比较复杂,特别对编解码器具有高数据吞吐量要求的高分辨率图像处理难以达到实时实现,为此提出MQ算术编码的硬件快速算法。首先分析了JPEG2000标准中MQ编码算法流程,然后提出了一种四级流水线结构的硬件实现。实验结果表明,根据所提出的硬件结构,编码器在Altera的EP1S25B672上最高运行速度能够达到65MHz,共占用了1051个LE资源,以较少的资源取得了较高的数据吞吐量。     

JPEG2000 MQ编码算法的优化和FPGA实现

MQ编码是一种无损数据压缩技术,已被JPEG2000标准采用,其高复杂度成为JPEG2000系统实现的速度瓶颈。本文在分析MQ编码算法软件流程的基础上提出了一种优化的基于流水线处理的MQ编码算法;并利用Xilinx FPGA的可编程特性详细地将此算法模块化,最后实现仿真验证。结果表明,该算法在有限资源消耗情况下最高运算时钟频率可达89.8MHz,算法对于压缩速度要求严格的JPEG2000实现具有一定实用价值。     

多跳无线网络通用网络编码结构研究

编码结构是决定运用网络编码与否的一个重要因素.根据多跳无线网络的特点,在现有的网络编码结构的基础之上,提出三种可以在无线网络中进行网络编码的通用编码结构:泛I型、泛Y型和泛X型结构.研究了网络节点对于这三种编码结构的发现、编码和解码的具体算法和过程,并对所提出的三种通用编码结构的编码有效性进行了实验仿真,仿真结果表明,编码结构的使用可以有效提升无线网络的平均吞吐量.     

位平面算术编码的编码分离与MQ编码器改进

为了降低图像压缩中位平面算术编码的计算复杂度,提出了将算术编码从位平面扫描中分离,方便编码的并行计算。以JPEG2000的位平面编码为例,实现了位平面扫描和MQ编码的分离,然后根据编码分离后的算法特点,设计了一种改进的MQ编码器。对该算法在TMS320C6000系列DSP中的实现进行了研究,通过软件流水、循环展开、条件操作和优化选项等方法提高处理速度。编码独立和编码器改进相结合,使重建图像质量稍有提高,编码速度提高了8倍以上。     

H.264编码器存储带宽分析及DRAM控制器设计

在分析H.264/AVC编码过程中存储器带宽需求的基础上,提出一种DRAM控制器结构,并实现了几种不同调度策略的DRAM控制器结构设计。实现了令牌环、固定优先级和抢占式等三种结构,结合已有的存储空间映射方法,通过减少换行及Bank切换过程中的冗余周期,进一步提高存储器的带宽利用率。实验结果表明,提出的三种存储器结构中抢占式调度具有最高的宽利用率,可满足150 MHz时钟频率条件下HDTV1080P实时编码的应用。     

多信息分段电子编码方法和系统

基于对目前已有编码系统的分析,提出了一种多信息分段电子编码方法和系统.它使用自定义信息段编码方法,不同信息段表示不同的信息类别,段内定义分段编码规则,各段组合成为整体编码.系统包括三个部分:信息分段定义、编码过程和解码过程,详细介绍了各部分内容及运行机制.与现有系统相比,多信息分段电子编码信息相关度高,编码框架统一且结构可配置、服务可定制、长度可变,较易兼容其他编码体系,可使用统一的编码解码软件,方便根据应用需求进行扩展.     

VVC帧间编码CU快速划分算法

通用视频编码(VVC)使用的四叉树加多叉树的块划分结构使编码过程的运算复杂度极高,这给编码器的实际应用带来了困难.为了解决这一问题,提出了一种基于时空域信息的编码单元(coding unit,CU)快速划分算法.该算法分为两部分,第一部分根据当前编码CU的形状,使用三种不同的模型在参考帧对应区域提取运动矢量,根据模型中...     

基于JPEG2000的一次性扫描、高效编码算法的研究

JPEG2000的算法的复杂性限制了它的优势的发挥。EBCOT是JPEG2000系统中占运算时间最多的组成部分,它对每个位平面进行三次扫描、进行三个编码通道的编码操作,浪费了大量的运算时间。针对这种情况,文中应用一次扫描完成三个编码通道编码操作的算法对其进行改进,在一次扫描过程中对位平面的所有系数进行编码。针对此算法引出的问题:首先,应用两个重要性状态变量代替原算法中的一个重要性状态变量;其次,采用“对称映射”形成上下文;最后,对三个编码通道的MQ编码器状态和上下文状态分别进行存储。这样三个编码通道可以顺序编码而不互相干扰,大大减少了运算时间,但仍保持了JPEG2000的优异性能。     

基于JPEG2000的图像联合压缩加密算法

为实现图像的压缩和加密同步,在深入研究MQ算术编码器的基础上,将Lorenz混沌系统生成的随机序列作为流密钥对JPEG2000压缩算法中比特平面编码形成的上下文和判决进行修正,以改变MQ编码时的概率分布来使得输出的码流发生变化,从而实现图像联合压缩加密.阐述了上下文修正和判决修正加密算法的规则.对算法进行仿真,结果表明,相对于原始压缩算法,所提出的算法对图像的压缩效率几乎没有影响,且安全性好、实时性高.     

A Data-Parallel Approach for Real-Time MPEG-2 Video Encoding

In this paper, we present a fine-grained parallel implementation of the MPEG-2 video encoder an the Intel Paragon XP/S parallel computer. We use a data-parallel approach and exploit parallelism within each frame, unlike some of the previous approaches that employ multiple processing of several disjoint video sequences. This makes our encoder suitable for real-time applications where the complete video sequence may not be present on the disk and may become available on a frame-by-frame basis with time. The Express parallel programming environment is employed as the underlying message-passing system making our encoder portable across a wide range of parallel and distributed architectures. The encoder also provides control over various parameters such as the number of processors in each dimension, the size of the motion search window, buffer management, and bitrate. Moreover, it has the flexibility to allow the inclusion of fast and new algorithms for different stages of the codec into the program, replacing current algorithms. Comparisons of execution times, speedups, and frame encoding rates using different numbers of processors are provided. An analysis of frame data distribution among multiple processors is also presented. In addition, our study reveals the degrees of parallelism and bottlenecks in the various computational modules of the MPEG-2 algorithm. We have used two motion estimation techniques and five different video sequences for our experiments. Using maximum parallelism by dividing one block per processor, an encoding rate higher than 30 frames/s has been achieved.     

基于多条带HEVC并行编码器的负载均衡算法

针对在均匀条带划分的HEVC并行视频编码器中出现的负载失衡问题,提出了一种基于多条带HEVC并行编码器的负载均衡算法。从编码参数入手,通过分析量化参数、参考帧数目和图像组等因素与编码耗时之间的关系,提出了一种基于编码参数的编码时间预测模型。以位置上和时间层上相邻已编码帧的编码信息为基础,以实际编码参数为依据,根据编码时间预测模型进行当前帧编码时间的预测,从而以当前帧的预测时间为依据,进行多条带HEVC并行编码器的负载均衡操作。实验结果表明,与现有均匀条带划分方法相比,提出的方法能够提升加速比9.23%左右,而编码的性能损失几乎可以忽略不计。     

Parallel CRC generation

Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out     

Real-time compression architecture for efficient coding in autostereoscopic displays

Integral imaging is a promising technique for delivering high-quality three-dimensional content. However, the large amounts of data produced during acquisition prohibits direct transmission of Integral Image data. A number of highly efficient compression architectures are proposed today that outperform standard two-dimensional encoding schemes. However, critical issues regarding real-time compression for quality demanding applications are a primary concern to currently existing Integral Image encoders. In this work we propose a real-time FPGA-based encoder for Integral Image and integral video content transmission. The proposed encoder is based on a highly efficient compression algorithm used in Integral Imaging applications. Real-time performance is achieved by realizing a pipelined architecture, taking into account the specific structure of an Integral Image. The required memory access operations are minimized by adopting a systolic concept of data flow through the core processing elements, further increasing the performance boost. The encoder targets, real-time, broadcast-type high-resolution Integral Image and video sequences and performs three orders of magnitude faster than the analogous software approach.     

AVS编码器Slice并行处理算法研究与实现

介绍了一种基于多slice的并行AVS 实时编码器的算法研究与实现, 基于slice的并行编码的优点是处理速度快、延迟小和数据处理简单,缺点是条纹效应。介绍了一种对基于slice的并行编码带来的条纹效应缺点进行改进的方法。实验结果表明,实现标清AVS 实时编码器是可行的。     

Development of an ultra-HD HEVC encoder using SIMD implementation and fast encoding schemes for smart surveillance system

High efficiency video coding (HEVC) is the newest video coding standard that can support powerful video compression performance with increased picture resolution for ultrahigh definition (UHD). Compared to the previous standard, HEVC achieved a coding efficiency double with a tremendous increase in encoder computational complexity, making support of commercial applications for UHD video service difficult. Especially, optimized HEVC encoder for UHD is expected to be deployed as a key technology for an emerging smart surveillance system in Internet of Things environment. Single-instruction-multiple-data implementation on an Intel x86 processor and several fast encoding schemes were investigated for the complexity reduction of the HEVC reference model (HM) encoder. Fast encoding schemes included early termination processes and data-level parallel processing. The computational complexity of the proposed HEVC encoder was decreased by approximately 192 times compared with HM encoder with an acceptable coding loss.     

一种基于帧间和帧内宏块级的X264并行编码算法

结合H.264编码标准对X264编码器进行了分析与研究,目的在于提高编码速度,增强X264的实时性。在重点分析了宏块间数据依赖关系的情况下,针对帧间宏块级多线程并行编码的特点,本文提出了一种基于帧间和帧内宏块级的多线程并行编码算法。该算法在原有的帧间宏块级多线程并行编码的基础上,遵循宏块之间的空间相关性,为I帧内每行宏块创建单独的线程,实现了帧间和帧内宏块级并行编码,达到了多粒度并行的效果。实验结果表明,该算法在视频序列能够有效地编码和保持峰值信噪比变化不大的情况下,提高了编码的加速比,从而加强了视频编码的实时性。     

High-performance JPEG 2000 encoder with rate-distortion optimization

An 81 MSamples/s JPEG 2000 single-chip encoder is implemented on 5.5 mm/sup 2/ area using 0.25-/spl mu/m CMOS technology. This IC can losslessly encode HDTV 720p resolution at 30 frames/s in real time. Three techniques are adopted: line-based discrete wavelet transform, parallel embedded block coding, and precompression rate-distortion optimization. The line-based discrete wavelet transform achieves the minimum external memory access, while the internal memory is reduced by a proper memory access scheme. The parallel embedded block coding increases the throughput and reduces the memory bandwidth with similar hardware cost comparing to conventional architectures. By accurately estimating bit rates, the precompression rate-distortion optimization reduces the required computational power and processing time of the embedded block coding since the code-blocks are truncated before compression. Experimental results show that this encoder has the highest throughput with the smallest area compared with other designs in the literature.     

H.26L视频编码器并行性分析与实现

文中对H.26L的并行性进行了分析，提出了几种不同的并行调度策略，以实现视频编码的实时处理。首先对H．26L编码器新特点进行了简单的介绍，然后从不同的层次提出了几种不同的并行调度策略并作了相应的分析；最后给出了其中一种并行调度的实现及其在COW上的试验结果。