Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

Edge chipping of silicon wafers in diamond grinding

Although diamond grinding is the most commonly used machining technique in silicon wafer thinning, it often induces edge chipping which leads to wafer breakage. This study investigates edge chipping of silicon wafer in diamond grinding. The study correlates edge chipping with the crystallographic orientation and thickness of a silicon wafer, as well as grinding process conditions, such as wheel grit size, grinding mode and feed rate. It identifies edge chipping in terms of critical thickness, geometry and dimensions. The study discusses the mechanisms of edge chipping based on machining mechanics and energy theories. Conclusions are drawn to summarize the study.     

Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Microstructure studies of the grinding damage in monocrystalline silicon wafers

1. Introduction The monocrystalline silicon wafer, as an impor-tant substrate of the integrated circuit, is widely used in IC manufacturing. Various processes are needed to transfer a silicon crystal ingot into wafers. Silicon crystallizes in the diamond lattice, with covalent bonding, ensuring an extremely stable spatial ar-rangement of the Si atoms in the monocrystal. It is a brittle material. Most processes can induce me-chanical damage. The depth and nature of the sub-surface damage will…     

ELID grinding of silicon wafers: A literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.     

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.     

A study on surface grinding of 300 mm silicon wafers

Most of today's IC chips are made from 200 mm or 150 mm silicon wafers. It is estimated that the transition from 200 mm to 300 mm wafers will bring a die cost saving of 30–40%. To meet their customers' needs, silicon wafer manufacturers are actively searching for cost-effective ways to manufacture 300 mm wafers with high quality. This paper presents the results of a study on surface grinding of 300 mm silicon wafers. In this study, a three-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feedrate). The process outputs studied include spindle motor current, surface roughness, grinding marks and depth of subsurface cracks.     

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

硅片自旋转磨削损伤深度的试验研究

基于自旋转磨削原理的硅片超精密磨床,采用角度抛光法和分步蚀刻法检测了树脂结合剂金刚石砂轮磨削硅片的损伤深度,利用方差分析法研究了砂轮粒度、工作台转速、砂轮进给率和砂轮转速等磨削参数对硅片损伤深度的影响规律.结果表明:磨削参数对硅片损伤深度的影响程度由大到小依次为砂轮粒度、砂轮进给率、砂轮转速和工作台转速.当砂轮的磨粒尺寸从40 μm减小到4 μm时,硅片的损伤深度从16.4 μm逐渐减小至0.8 μm.在一定的范围内,当其它磨削参数不变时,硅片的损伤深度随着砂轮进给率的增大而增大,随着砂轮转速的增大而减小,随着工作台转速的增大而减小.     

金刚石砂轮磨削贴膜硅片崩边的研究

用树脂结合剂金刚石砂轮将贴膜厚度为80 μm和160 μm的单晶硅片减薄到400 μm,通过测量硅片边缘的崩边尺寸评价贴膜对硅片加工质量的影响。试验结果表明:硅片贴膜能有效降低硅片碎片率;当硅片未贴膜时,硅片的平均崩边尺寸为3.08 μm,当硅片贴膜厚度为80 μm和160 μm时,硅片的平均崩边尺寸为4.61 μm和3.60 μm;即硅片贴膜磨削对硅片崩边有恶化作用,但该影响较小,用厚膜时恶化程度可控制在20%以内。且用23 μm金刚石砂轮减薄磨削贴膜硅片时,硅片<110>晶向和<100>晶向的崩边尺寸无明显差异。      

Fine grinding of silicon wafers: machine configurations for spindle angle adjustments

This paper addresses an important aspect of silicon wafer fine grinding: machine design. For any commercially available wafer grinders, spindle angle adjustments based on the wafer shape ground is almost inevitable in order to achieve flat wafers. However, there has been no commonly accepted guidance for the design of machine configurations to ensure the easiest adjustment. Practitioners doing spindle angle adjustments have been frustrated by the difficulties of achieving the adjustments on commercial wafer grinders. This paper first illustrates such difficulties with a machine configuration frequently cited in the literature. It then demonstrates the potential ease of spindle angle adjustments with a proposed machine configuration. Next, it shows mathematically that the proposed configuration (specifically, a pair of the axes for spindle angle adjustments) is uniquely determined once the wheel diameter and wafer diameter are known. It also shows that the proposed configuration is the best in terms of ease in spindle angle adjustments. The spindle angle adjustments will be more difficult with any other configurations deviating from the proposed one.     

硅片纳米磨削过程中磨粒切削深度的测量

分析了硅片纳米磨削过程中磨粒切削深度的特点,采用基于扫描白光干涉原理的三维表面轮廓仪对磨削后硅片表面的磨削沟槽的深度和宽度进行了测量,进而对磨削沟槽的深度和未变形切屑的横截面的宽高比进行了统计分析。研究表明,采用硅片自旋转磨削方法对硅片进行纳米磨削时,参与切削的磨粒数量极少,起主要切削作用的磨粒只占有效磨粒数量的一小部分,此部分磨粒的切削深度大于砂轮的切削深度,甚至可达后者的2倍;未变形切屑的截面为三角形,其宽高比在21～153之间,平均值为69。     

超精密磨削加工微小振动模拟系统研究

文章分析了加工过程中产生的振动现象以及砂轮振动对工件表面精度的影响,设计了超精密磨削加工砂轮微振动的模拟系统.该系统可模拟实际磨削过程中砂轮径向、横向的微小振动和摆动,为研究不同的磨削加工参数下砂轮的振动及其对工件表面精度的影响奠定了实验基础.     

Fine grinding of silicon wafers: a mathematical model for the chuck shape

Fine grinding of silicon wafers is a patented technology to manufacture super flat semiconductor wafers cost-effectively. Two papers on fine grinding were previously published in this journal, one discussed its uniqueness and special requirements, and the other presented the results of a designed experimental investigation. As a follow up, this paper presents a study aiming at overcoming one of the technical barriers that have hindered the widespread application of this technology, namely, the difficulty and uncertainty in chuck preparation. Although the chuck shape is critically important in fine grinding, there are no standard procedures for its preparation. Furthermore, the information on the relation between the set-up parameters and the resulting chuck shape is not readily available. In this paper, a mathematical model for the chuck shape is first developed. Then the model is used to predict the relations between the chuck shape and the set-up parameters. Finally, the results of the pilot experiments to verify the model are discussed.     

Finite element analysis for grinding of wire-sawn silicon wafers: a designed experiment

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. This paper presents the results of a finite element analysis for grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of four factors (wafer thickness, waviness wavelength, waviness height and grinding force) on effectiveness of waviness reduction. The implications of this study to manufacturing are also discussed.     

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

A study on ELID ultra precision grinding of optical glass with acoustic emission

ELID grinding of BK7 glass and Zerodur was investigated using acoustic emission. Experiments showed that the contacting area between the wheel and workpiece in a grinding process was critical to influence wheel loading for a fine grit size resin-bonded cup wheel. ELID can be used for efficient material removal when the wheel/workpiece contacting area is large. Correlations were observed between the dressing intensity on the ELID wheel and the detected AE signals. Aggressive ELID dressing parameters for grinding with finer grit size wheels corresponded to a lower AE level. With an increase in the processing time of an ELID wheel, low and stable AE amplitudes became large with fluctuations due to the deterioration of the grinding wheel. Results indicate that the AE sensing technique has the potential to be adopted as an effective method for monitoring an ultra precision grinding process, identifying the condition of the grinding wheel and investigating the mechanism of ELID grinding.     

An experimental study of flat fixed abrasive grinding of silicon wafers using resin-bonded diamond pellets

The purpose of this paper is to investigate the effect of the diamond grain size, the wheel rotation speed, the table rotation speed, and the applied pressure in the vertical flat grinding on the surface roughness of silicon wafers using Taguchi orthogonal array design. Besides, the pits and resistivity on the wafers were studied as well. The experiment results showed that the diamond grain size and the wheel rotation speed of the vertical flat grinding for the roughness of wafers obtained are the relatively larger significant contribution. When the smaller diamond grit size, the faster wheel rotation speed, the faster table rotation speed, and the smaller applied pressure in the flat grinding are employed, the traces produced by the grains are denser and the chip thickness and the depth of cut were smaller, which cause the silicon wafer to produce the higher degree of the ductile grinding. This will lead the wafer surface to produce the smaller amount and size of the pits, thereby generating the lower surface roughness. In addition, the center site of the wafer obtained is the smaller amount and size of the pits than the outer of the wafer, which produces the better surface roughness and the lower resistivity.