共查询到19条相似文献,搜索用时 78 毫秒
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本文设计了应用SCL、TPSC和CMOS静态三种类型的触发器配合工作的新型双模预分频器。与传统使用单一种类型触发器的双模预分频器相比,该双模预分频器更容易获得高速、宽带、低功耗和低相位噪声的性能。为了验证此设计的性能,采用了SMIC 0.18um CMOS 工艺流片实现。在电源电压为1.8V的条件下测试,此双模预分频器的工作频率范围从0.9 GHz 到 3.4 GHz ;当输入信号为 3.4 GHz时,其功耗为2.51mW,相位噪声为-134.78 dBc/Hz @ 1 MHz. 其核心面积为 is 57um*30um。鉴于其良好的性能,可以应用于许多射频系统的频率综合器中,特别在多标准无线通信系统中。 相似文献
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一种具有自适应节能的新型4/5高速双模预分频器 总被引:1,自引:1,他引:0
首次提出一种自适应节能方法用于设计4/5高速双模预分频器,它的特点是工作在除4模式时,其中一个D类触发器处于休眠状态.使用台积电混合信号0.25μm CMOS工艺,采用这一自适应节能的设计方法,设计了一个具有源极耦合结构的4/5高速舣模预分频器.仿真结果证明,这一新型4/5高速双模预分频器不受休眠到工作转换状态的影响,最高工作频率保持不变.同时,流片结果表明,当这一新型高速预分频器用于实现66/67分频时,可节省高达20%以上的功耗. 相似文献
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<正> 在许多世界著名的半导体制造公司开发的型号繁多的单片机芯片内部,定时器/计数器模块是一种基本上普遍配置的常用外围设备模块,只是配备的数量和规格不同而已。所谓的规格不同,指的是宽度的不同、是否附带着预分频器、是否附带着后分频器、是否同时附带着预分频器和后分频器、预分频器或后分频器的分频比的不同,等等。 相似文献
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描述了一个应用于高集成度2 GHz频率综合器的预分频电路的设计,预分频电路中D触发器采用了源极耦合逻辑电路结构,可以提高电路工作频率,同时有效减小开关噪声和电路功耗.预分频电路采用TSMC 0.25 μm IPSM CMOS工艺实现,Spectre仿真表明,在1.8 V的电源电压下,经过优化的预分频电路能够在各种工艺条件和温度下正常工作,整体功耗为6.2 mw(单个D触发器功耗仅为1.8 mW),满足手持设备的要求. 相似文献
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根据IEEE 802.3ae XAUI协议中锁相环的设计指标,基于65 nm CMOS工艺,设计实现了一种高速可编程整数分频器。采用高性能D型触发器对压控振荡器输出时钟进行预分频,分频器由4/5双模预分频器、2 Bit和5 Bit计数器组成,可实现8~131的连续分频比。[JP]仿真结果表明,在1 V供电条件下,分频器最高工作频率可达4.375 GHz,消耗电流<0.4 mA。 相似文献
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采用南京电子器件研究所4英吋0.25μmGa AsPHEMT工艺技术,设计、制作Ku波段Ga AsMMIC六位数控移相器芯片,芯片尺寸为3mm×1.1mm×0.1mm。在15~17GHz设计频带内,该移相器具有优良的电性能,插入损耗小于9dB,移相精度(RMS)小于1°,输入输出电压驻波比小于1.4。 相似文献
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A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz 相似文献
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The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown. 相似文献
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A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 μm CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for the high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage 相似文献
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Kurisu M. Ohuchi M. Sawairi A. Sugiyama M. Takemura H. Tashiro T. 《Solid-State Circuits, IEEE Journal of》1991,26(11):1626-1631
A silicon bipolar divide-by-eight static frequency divider was developed. A state-of-the-art advanced borosilicate-glass self-aligned (A-BSA) transistor technology that has a cutoff frequency of 40 GHz at V ce=1 V was applied. Optimum circuit and layout designs were carried out for high-speed/low-power operation. The single-ended input realized by an on-chip metal-insulator-metal (MIM) capacitor makes it easy to use in microwave applications. Ultrahigh-speed operation, up to 21 GHz, was realized, with 320-mW power dissipation from a single +5-V supply. The static frequency divider is a suitable prescaler for phase-locked oscillators (PLOs), completely covering microwave frequencies from L band through Ku band (1-18 GHz) 相似文献
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《Solid-State Circuits, IEEE Journal of》1993,28(4):513-517
An extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus prescaler that operates at up to 1 GHz and dissipates 0.9 mW at a supply voltage of 1 V is presented. The prescaler is capable of 2-GHz performance with dissipation of 7.2 mW at 2 V. This superior performance is primarily achieved by using an advanced ultrathin-film CMOS/SIMOX process technology combined with a circuit configuration that uses a divide-by-2/3 synchronous counter. Using these same technologies, a single-chip CMOS phase-locked-loop (PLL) LSI that uses the developed prescaler was fabricated. It can operate at up to 2 GHz while dissipating only 8.4 mW at a supply voltage of 2 V. Even at a lower supply voltage of 1.2 V, 1-GHz operation can be obtained with a corresponding power consumption of 1.4 mW. These results indicate that the high-speed and very-low-power features of CMOS/SIMOX technology could have an important impact on the development of future personal communication systems 相似文献
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A triple-modulus phase-switching prescaler for high- speed operations is presented in this paper. By reversing the switching orders between the eight 45deg-spaced signals generated by the 8 : 1 frequency divider, the maximum operating frequency of the prescaler is effectively enhanced. With the triple-modulus switching scheme, a wide frequency covering range is achieved. The proposed prescaler is implemented in a 0.18-mum CMOS process, demonstrating a maximum operating frequency of 16 GHz without additional peaking inductors for a compact chip size. Based on the high-speed prescaler, a fully integrated integer-N frequency synthesizer is realized. The synthesizer operates at an output frequency from 13.9 to 15.6 GHz, making it very attractive for wideband applications in Ku-band. At an output frequency of 14.4 GHz, the measured sideband power and phase noise at 1-MHz offset are -60 dBc and -103.8 dBc/Hz, respectively. The fabricated circuit occupies a chip area of 1 mm2 and consumes a dc power of 70 mW from a 1.8-V supply voltage 相似文献
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Maeda T. Wada S. Tokushima M. Ishikawa M. Yamazaki J. Fujii M. 《Solid-State Circuits, IEEE Journal of》1999,34(2):212-218
A GaAs divide-by-256/258 dual-modulus static prescaler is described. The prescaler has a pulse-swallow counter-type architecture and quasi-differential switch flip-flops as its basic circuit architecture. For the input buffer circuit, a circuit called a source-coupled push-pull circuit has been developed that can generate high-frequency complementary signals from a single-phase signal at a low supply voltage. This IC operates at up to 14.5 GHz with a power consumption of 22 mW. The power consumption is less than 1/50 of the previously reported prescalers that can operate above 10 GHz 相似文献
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《Microwave Theory and Techniques》1987,35(10):917-918
A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW. 相似文献