High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

Improvement of the Performance of TiHfO MIM Capacitors by Using a Dual Plasma Treatment of the Lower Electrode

We show that a conventional nitrogen plasma treatment is insufficient to suppress the formation of an interfacial layer at the bottom electrode of TiHfO metal-insulator-metal (MIM) capacitors. However, the capacitance density and leakage current of TaN/TiHfO/TaN MIM capacitors monotonically improve by exposing the lower TaN electrode to an additional oxygen plasma treatment. By performing dual oxygen and nitrogen plasma treatments on the lower electrode, the leakage current was 4.8 times 10^-6 A/cm² (at -1 V) at a 28 fF/ mum² capacitance density.     

Border-Trap Characterization in High-κ Strained-Si MOSFETs

In this letter, we focus on the border-trap characterization of TaN/HfO₂/Si and TaN/HfO₂/strained-Si/Si_0.8Ge_0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si_0.8Ge_0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.     

Performance Improvement of $hbox{Sm}_{2}hbox{O}_{3}$ MIM Capacitors by Using Plasma Treatment After Dielectric Formation

In this letter, we investigate the dependence of the performance of metal-insulator-metal (MIM) capacitors with Sm₂O₃ dielectric on plasma treatment (PT) performed before Sm₂O₃ deposition, after Sm₂O₃ deposition, or both before and after Sm₂O₃ deposition. By performing PT in N₂ ambient (PTN) after Sm₂O₃ dielectric formation, the effective quadratic voltage coefficient of capacitance (VCC) can be reduced from 498 to 234 ppm/V² and the effective linear VCC can be reduced from 742.3 to 172 ppm/V for MIM capacitor with Sm₂O₃ dielectric having a capacitance density of ~ 7.5 fF/mum². The leakage current density at +3.3 V can be reduced from 3.44 10^-7 to 1.60 times 10^-8 A/cm² by performing PTN in both before and after Sm₂O₃ deposition. PTN after dielectric formation is an effective way to improve the performance of high-kappa dielectric MIM capacitors for RF and analog/mixed signal IC applications.     

High-Permittivity Dielectric Stack on Gallium Nitride Formed by Silane Surface Passivation and Metal–Organic Chemical Vapor Deposition

We report the first demonstration of an in situ surface-passivation technology for a GaN substrate using vacuum anneal (VA) and silane ( SiH₄) treatment in a metal-organic chemical vapor deposition multichamber tool. Excellent electrical properties were obtained for TaN/HfAlO/GaN capacitors. Interface state density D_it was measured from midgap to near-conduction-band edge (E_C) using the conductance method at high temperatures, and the lowest D_it of 1 × 10¹¹ cm^-2 · eV^-1 at the midgap was achieved. Multiple frequency capacitance-voltage (C-V) measurement (10, 400, and 500 kHz) showed little frequency dispersion. Furthermore, the TaN/HfAlO/GaN stack was studied using high-resolution transmission electron microscopy, and the effectiveness of passivation using VA and SiH₄ was evaluated using high-resolution X-ray photoelectron spectroscopy. The method reported here effectively removes the native oxide and passivates the GaN surface during the high-k dielectric-deposition process.     

Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Stress Engineering in High-$kappa$ FETs for Mobility and On-Current Enhancements

We present a systematic study of uniaxial/biaxial stress effects on low-field mobility and on-current in high-kappa n/pFETs. It is found that mobility enhancement by strain in high-kappa FETs is smaller than SiO₂ FETs in low effective field because of remote Coulomb scattering caused by fixed charges inside high-kappa films, while mobility enhancement by biaxial tensile strain in high-kappa nFETs is greater than SiO₂ nFETs in high effective field due to weaker surface roughness scattering in high-kappa nFETs. In short-channel high-kappa nFETs, better on-current improvement by biaxial tensile strain than in SiO₂ nFETs is achieved as a result of both higher mobility enhancement and weaker velocity saturation. The optimum stress design for high-kappa n/pFETs is also discussed, and it is concluded that the application of transverse tensile stress, in addition to conventional longitudinal stress, is essential for performance improvement of high-kappa n/pFETs.     

Low Subthreshold Swing HfLaO/Pentacene Organic Thin-Film Transistors

We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of -1.3 V, and a field-effect mobility of 0.71cm²/ Vldrs . This occurred along with an ON-OFF state drive current ratio of 1.0 times 10⁵, when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm² that is given by the HfLaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 times 10^-7 at 2 V.     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

High-κ Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality—A Mobility Study

The effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities are examined for SiO₂/HfO₂/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-kappa bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 degC spike for t=1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 degC for t=60 s). For 1000 degC spike-annealed films, where the highest SiO₂/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO₂ and the IL which increases for high-temperature processing     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

High-Temperature Leakage Improvement in Metal–Insulator–Metal Capacitors by Work–Function Tuning

Using low-cost and high work-function Ni, a low leakage current of 5times10^-6 A/cm² at 125 degC is obtained in a high 25-fF/mum²-density SrTiO₃ metal-insulator-metal (MIM) capacitor processed at 400 degC. This is approximately two orders of magnitude better than the same device using a TaN electrode, with added advantages of improved voltage and temperature coefficients of capacitance. This work-function tuning method also has merit for achieving both low thermal leakage and high overall kappa value beyond previous laminate structure     

Effect of bottom electrode materials on the electrical andreliability characteristics of (Ba, Sr)TiO3 capacitors

The dielectric constant and the leakage current density of (Ba, Sr)TiO₃ (BST) thin films deposited on various bottom electrode materials (Pt, Ir, IrO₂/Ir, Ru, RuO₂/Ru) before and after annealing in O₂ ambient were investigated. The improvement of crystallinity of BST films deposited on various bottom electrodes was observed after the postannealing process. The dielectric constant and leakage current of the films mere also strongly dependent on the postannealing conditions. BST thin film deposited on Ir bottom electrode at 500°C, after 700°C annealing in O₂ for 20 min, has the dielectric constant of 593, a loss tangent of 0.019 at 100 kHz, a leakage current density of 1.9×10 ^-8 A/cm² at an electric field of 200 kV/cm with a delay time of 30 s, and a charge storage density of 53 fC/μm² at an applied field of 100 kV/cm. The BST films deposited on Ir with post-annealing can obtain better dielectric properties than on other bottom electrodes in our experiments. And Ru electrode is unstable because the interdiffusion of Ru and Ti occurs at the interface between the BST and Ru after postannealing. The ten year lifetime of time-dependent dielectric breakdown (TDDB) studies indicate that BST on Pt, Ir, IrO₂/Ir, Ru, and RuO₂/Ru have long lifetimes over ten gears on operation at the voltage bias of 2 V     

Room-Temperature Deposited Titanium Silicate Thin Films for MIM Capacitor Applications

High-k titanium silicate (i.e., TiSiO₄) thin films of various thicknesses (in the 4.5- to 160-nm range) were successfully deposited by means of a sputter deposition process at room-temperature and integrated into metal-insulator-metal (MIM) capacitors. It is shown that the TiSiO₄-based capacitors can exhibit a capacitance density as high as 30 fF/mum² while maintaining low dielectric dispersion and losses. An excellent voltage linearity was also obtained ( alpha~600 ppm/V² at 8.2 fF/mum²) together with a high dielectric constant of 16.5 and low leakage current of about 10 nA/cm² at 1 MV/cm. Our results thus show that TiSiO₄ films constitute a very promising approach for the achievement of high performance MIM capacitors     

Reactively sputtered tantalum pentoxide thin films for integrated capacitors

The aim of this work was to develop a deposition process for a high-dielectric constant tantalum pentoxide for integrated capacitors. Thin films were deposited reactively on glass wafers using a radio-frequency magnetron sputtering cluster tool at various O₂/Ar flow ratios. By using 2 MeV ⁴He⁺ backscattering spectroscopy and X-ray diffraction, the films obtained showed a stoichiometric orthorhombic β-Ta₂O₅ phase at 20% O₂ in the sputtering gas flow. With low-frequency measurements (f=100 kHz), a 200×200-μm² square metal–insulator–metal (MIM) capacitor with copper electrodes and a 340-nm thick dielectric gave a capacitance density of 0.066 μF/cm², with a quality factor (Q) of 650. The value of the relative permittivity (_r) was approximately 25 determined from MIM capacitors of various sizes. The surface roughness of the 376-nm thick oxide film was found to be small: 0.255 nm. The largest measured capacitor (200×200 μm²) gave reasonable results at low frequencies. When the frequency was increased (100 kHz–20 GHz) only for the smaller capacitors (30×30 μm²) the capacitance remained constant. However, the Q values decreased of the smaller capacitors as a function of frequency. Processed tantalum pentoxide MIM capacitors possessed reasonable electrical properties below 2 GHz and good potential for further improvement.     

Work-Function Tuning of TaN by High-Temperature Metal Intermixing Technique for Gate-First CMOS Process

This letter investigates the feasibility of adjusting the work function (WF) of TaN metal gate by intermixing (InM) of ultra-thin TaN/Metal stacks at high temperature. This could be useful for the integration of dual-WF metal gates in a gate-first CMOS process without exposing gate dielectric during metal-etching process. TaN/Tb and TaN/Ir stacks were studied, and it is found that the WF of TaN can be readily modulated through metal InM in TaN/Tb stack after high-temperature treatment$(sim$1000$^circhboxC)$, which simulates the source/drain dopant activation process in a gate-first CMOS process. Factors affecting the InM process will be discussed. Successful transistor threshold voltage adjustment by$sim$300 mV on high-$kappa$$hboxHfTaON/HfO_2$dielectrics has also been demonstrated in TaN/Tb stack using this technique.     

A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

A 1/3-inch, 800^H x 600^v pixels, 5.6 x 5.6 mum² color CMOS image sensor with three photocurrent integrations in pixel photodiodes, pixel lateral overflow capacitors and column capacitors fabricated in a 0.18 mum 2P3M CMOS technology has been reported. The image sensor operates using photodiode integrations and lateral overflow integrations in low light condition and achieves a wide dynamic range (DR) performance of around 100 dB in its one exposure. The wide DR performance in one exposure makes high S/N ratios at the signal switching points in the multiple exposures. The CMOS image sensor also operates using the column capacitor integration in very bright light condition. In the column capacitor integration, the photocurrents generated at the photodiodes are directly integrated at the column capacitors in each column line. The combination of two exposures using the photodiode integrations and the lateral overflow integrations and one exposure using the column capacitors leads to the whole linear photo-electric conversion responses from low light to very bright light region. The fabricated image sensor achieves a high S/N ratio, a fully linear response and over 180 dB DR in the incident light ranging from about 1.4 x 10^-2 lx to about 2.4 x 10⁷ lx.     

In Situ Comparison of Si/High- $kappa$ and $hbox{Si}/ hbox{SiO}_{2}$ Channel Properties in SOI MOSFETs

Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO₂ or HfSiON) and Si/SiO₂ interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO₂, the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.