The Computer-Aided Approach to Emission Testing

The use of the computer to obtain an Emission Measurement Automatic System (EMAS) is described. Major advantages are increased measurement accuracy and reduction of testing time and effort. Frequency accuracy better than 0.1 percent and amplitude accuracy (assuming an ideal calibrator) better than 0.5 dB have been demonstrated. The computer is used both for controlling the test execution and for off-line test results processing.     

伴随测试的有效途径

软件测试作为产品验证和确认不可或缺的重要手段,如果与开发过程融合在一起,对软件进行伴随测试,就能为开发过程的量化管理提供有效的数据,为软件质量的度量提供有力的支持。如何使软件测试有效地融入开发过程,从技术和非技术方面提出一些观点和解决途径,对有效地发挥软件测试应有的作用具有实际的意义。     

专用集成电路CAT技术的进展

本文简单地回顾了提高VLSI测试效率所采用的一些手段,讨论了在ASIC测试问题研究中出现的一些新观点、新方法、新动向,以及所取得的成果。在此基础上,文章阐明了ASIC测试技术的发展方向,并着重论述了可望在未来得到发展的,针对ASIC的功能测试方法。     

Computer-Aided Testing of Mixers Between 90 and 350 GHz

Two computer-controlled measurement systems have been constructed to allow testing of millimeter-wave Schottky-barrier diode mixers in the frequency range from 90 to 350 GHz. A theoretical background to mixer measurement is presented and the design of the instruments and associated computer software is described. In a companion paper, a typical application of the measurement system to the testing and evacuation of a practical W-band, cryogenic, fixed-tuned Schottky diode mixer is used to demonstrate the performance and versatility of the instruments.     

Test Fixtures for RF Susceptibility Testing

The most likely standard test fixture for RF susceptibility testing is the twin-strip transmission line, or its half-space counterpart. Its capacitance per meter (length) is 2? or 4?; characteristic impedance Zc= Z0/2 or Z0/4; voltage gradient Ez = V/w or 2 V/w; magnetic field Hy = V/w Z0 or 2 V/w Z0, respectively.     

A Parallel-Strip Line for Testing RF Susceptibility

This paper presents a technique for establishing known, high intensity RF fields suitable for testing the susceptibility of electronic equipment to these fields. The technique overcomes a deficiency in tests for radiated susceptibility which are required by military specifications, such as MIL-I-26600. Such tests fail to use field intensities that are representative of the environments in which electronic equipment will be installed. It is becoming more important not only to use realistic field strengths, but to know these field strengths to a fair degree of accuracy. The system designer will have more assurance of system compatibility if components have been tested to meet the requirements of the installation environment. A significant amount of time and money can be saved if susceptibility problems are recognized and solved prior to equipment installation.     

一种面向性质的实时系统测试方法

尽管Statecharts在反应式实时系统建模领域获得了广泛应用,基于Statecharts开发的实时软件的测试仍然十分困难.由于引入了时间维,待测系统的行为空间变得非常庞大,使得难以对其进行全面深入测试.本文提出了一种面向性质的实时系统测试方法.首先对UML Statecharts作适当实时扩展,使得扩展后能描述non-trivial时间约束;然后用一种受限实时逻辑描述待测系统的功能特性;在此基础上根据待测性质从系统模型生成有针对性的测试序列.实验表明,在相同测试深度下,面向性质测试比非面向性质测试需要少得多的测试序列.     

Parallel Wire Susceptibility Testing for Signal Lines

A technique is presented which can be utilized to establish a standardized procedure for performing conducted susceptibility testing on signal lines at the component and/or the subsystem level. Typical military specifications require that the test function be injected to the test lines via a susceptibility transformer, a coupling capacitor, or a standardized network, such as the line stabilization network (LSN). Although these methods may be adequate for testing of power line susceptibility, they present several disadvantages when utilized in signal lines, such as impedance loading, the requirement for physical insertion, and proximity to the load. These disadvantages become more pronounced at RF where the signal developed across the input of the test specimen may be considerably lower than the signal injected at the physical insertion point. A technique that overcomes these deficiencies utilizes a coupling jig that 1) does not require a physical connection, and 2) provides a known coupling across the input impedance of the package being tested-thus simulating, in a very realistic manner, interference coupling as it may occur in a system. A general expression for coupling prediction and a computer solution for various values of load impedances are presented.     

A New Approach to the Computer-Aided Design of Nonlinear Networks and its Application to Microwave Parametric Frequency Dividers

A new cost-effective method allowing nonlinear microwave circuits to be designed by computer is demonstrated by application to parametric frequency dividers. The method is based on frequency-domain representations of both nonlinear circuit components and network voltages and currents. A special optimization strategy determines the unknown parameters of the linear part of the circuit while estimating the need for a complete analysis of the nonlinear network at each step of the iterative process.     

Differential Thermal Testing: An Approach to its Feasibility

Testing techniques based on the functional behaviour, the propagation delay and the levels of quiescent current have been used with great success for the last two decade technologies. However, the efficiency of such techniques is dubious for future technologies, characterised by huge mixed-mode complex circuits and very low supply voltage levels. In this paper the feasibility of using internal thermal sensors to detect heat sources provoked by structural defects are considered and evaluated.     

一种新颖的FPGA逻辑故障测试定位方法

FPGA的生产测试是FPGA设计中非常重要的环节,不仅要求能够检测芯片是否发生故障,还必须进行精确的故障定位,以便设计人员对设计故障和工艺故障进行改进。依靠将CLB输出级联的方式进行故障定位,往往使测试激励在时序设计上变得更加复杂。灵活利用CLB周围的三态门资源,可以对FPGA逻辑故障进行快速准确的定位,且测试激励简洁。     

From Design Validation to Hardware Testing: A Unified Approach

In this paper we propose a new approach that addresses both the problems of design validation and hardware testing since the early stages of the design flow. The approach consists in adapting the mutation testing, a software method, to circuits described in VHDL. At the functional level, the approach behaves as a design validation method and at the hardware level as a classical ATPG. Standard software test metrics are used for assessing the quality of the design validation process, and the hardware fault coverage for assessing the test quality at the hardware level. An enhancement process that allows design validation to be efficiently reused for hardware testing is detailed. The approach is shown to be efficient upon a set of representative circuits.     

The Differential Susceptibility to Media Effects Model

In this theoretical article, we introduce the Differential Susceptibility to Media Effects Model (DSMM), a new, integrative model to improve our understanding of media effects. The DSMM organizes, integrates, and extends the insights developed in earlier microlevel media‐effects theories. It distinguishes 3 types of susceptibility to media effects: dispositional, developmental, and social susceptibility. Using the analogy of a mixing console, the DSMM proposes 3 media response states that mediate media effects: cognitive, emotional, and excitative. The assumptions on which the DSMM is based together explain (a) why some individuals are more highly susceptible to media effects than others, (b) how and why media influence those individuals, and (c) how media effects can be enhanced or counteracted.     

基于ATE的FPGA测试方法

本文以Xilinx公司基于SRAM的FPGA XC4010为研究对象,将FPGA配置成两种电路来完成对可编程逻辑模块(CLB)的测试,并阐述了如何在Teradyne商用ATE(Automatic Test Equipment)J750上实现FPGA的在线配置及测试,为FPGA面向应用的测试提供一种有效的方法.     

The Correlation Method for Computer-Aided Statistical Analysis

Computer-aided statistical analysis of electronic circuits, designed to predict the effects of component-part variability on circuit performance, provides extremely useful assistance in performing a circuit design. The correlation method, a new computer-oriented technique of statistical analysis, provides precise estimates of performance variability, high speed of computation, and the computation of the distribution laws of circuit performance characteristics at a generic time instant. Thus, the quantitative characteristics of reliability can be predicted as functions of time.     

An Information-Spectrum Approach to Classical and Quantum Hypothesis Testing for Simple Hypotheses

The information-spectrum analysis made by Han for classical hypothesis testing for simple hypotheses is extended to a unifying framework including both classical and quantum hypothesis testing. The results are also applied to fixed-length source coding when loosening the normalizing condition for probability distributions and for quantum states. We establish general formulas for several quantities relating to the asymptotic optimality of tests/codes in terms of classical and quantum information spectra     

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2 ⁿ × (2 ⁿ – 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.     

用于SOC测试的一种有效的BIST方法

为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测试实验数据表明,该BIST方法能有效提高测试覆盖率.     

A Novel Evolutionary Approach for Adaptive Random Testing

Random testing is a low cost strategy that can be applied to a wide range of testing problems. While the cost and straightforward application of random testing are appealing, these benefits must be evaluated against the reduced effectiveness due to the generality of the approach. Recently, a number of novel techniques, coined Adaptive Random Testing, have sought to increase the effectiveness of random testing by attempting to maximize the testing coverage of the input domain. This paper presents the novel application of an evolutionary search algorithm to this problem. The results of an extensive simulation study are presented in which the evolutionary approach is compared against the Fixed Size Candidate Set (FSCS), Restricted Random Testing (RRT), quasi-random testing using the Sobol sequence (Sobol), and random testing (RT) methods. The evolutionary approach was found to be superior to FSCS, RRT, Sobol, and RT amongst block patterns, the arena in which FSCS, and RRT have demonstrated the most appreciable gains in testing effectiveness. The results among fault patterns with increased complexity were shown to be similar to those of FSCS, and RRT; and showed a modest improvement over Sobol, and RT. A comparison of the asymptotic and empirical runtimes of the evolutionary search algorithm, and the other testing approaches, was also considered, providing further evidence that the application of an evolutionary search algorithm is feasible, and within the same order of time complexity as the other adaptive random testing approaches.