CMOS2.5 Gb/s时钟恢复电路设计

设计采用0.35μm CMOS工艺来实现一款CMOS2.5 Gb/s时钟恢复电路。由于0.35μm CMOS工艺的限制,采用了预处理电路加锁相环的电路结构。这种电路结构有利于单片集成且工作速度高。预处理器主要有延迟单元、乘法器和窄带滤波电路构成,可以从NRZ数据中得到时钟信号。锁相环采用二阶的模拟锁相环结构,鉴相器采用Gilbert乘法器,环路滤波器采用无源滤波器,VCO采用3级环形振荡器。     

一种基于SiGe工艺的ECL环形振荡器

介绍了一种基于SiGe平面集成电路工艺制作的ECL环形振荡器,采用15级反相器闭环结构,能够产生280 MHz高频振荡信号,振荡周期为3.58 ns,平均每级反相器延迟为119 ps。该电路结构简单、易集成、成本低,可广泛移植于各类片上系统,用作时钟信号源等。     

10Gb/s 0.18μm CMOS注入式时钟恢复电路

介绍了一种利用0.18μm CMOS工艺实现,用于SDH系统STM-64级别(10GHz)的时钟恢复电路。该电路采用注入式振荡器辅助锁相环的锁定。文中分析该电路的系统结构、单元电路结构和环路设计,并给出了模拟结果和版图。     

一种具有温度补偿的时钟振荡器设计

介绍了一种采用0.35μm CMOS工艺制作的具有温度补偿的时钟振荡器电路。从环形振荡器的基本原理出发,基于对CMOS工艺各种非理想性因素的分析,提出一种新型的工艺补偿电路,减小振荡器偏置电流随阈值电压的漂移;在延迟单元的设计中,引入NMOS交叉耦合对组成的交流负阻抗来进一步补偿PMOS迁移率随温度的变化,从而有效抑制输出频率随温度的变化。该振荡器电路用于MEMS加速度计读出电路芯片。样品电路测试结果表明,在-20~100℃温度范围内,时钟振荡器的频率仅变化38kHz。     

用于光探测和测量的环形振荡传感器

在集成电路中,时钟产生器和系统校准广泛采用环形振荡器。通过制造环形振荡器并测量它们的振荡频率,可以获取有关反相电路的传播延迟时间的直接信息。     

1.2V低功耗时钟发生器设计

基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现。电路使用1.2 V单一电源电压,并在片上集成了环路滤波器。其中,振荡器为电流控制、全差分结构的五级环形振荡器。该信号发生器可以产生的时钟频率范围为12.5～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk=75 ps,rms=8.6 ps;Cycle-to-Cycle抖动为:pk-pk=132 ps,rms=14.1 ps。电路的面积为84μm2。     

一种新型差分脉宽控制环路的设计

设计了一种新型时钟稳定电路～差分脉宽控制电路.用参考电路产生参考电压,避免因采用环形振荡器等方法产生大的时钟抖动.同时,在控制电路部分用交叉耦合正反馈来调节时钟占空比.该电路采用0.18 μm工艺,电源电压为1.9 V,输入时钟占空比调节范围为25%～75%,时钟频率为2 GHz,时钟抖动小于200 fs.     

SZ系列GaAs门电路应用研究

本文叙述了SZ系列GaAs超高速门电路结构、原理及超高频特性.针对阻抗匹配与高频时钟信号传输的关系等问题展开了深入的讨论,并给出了用SZ系列GaAs门电路搭制的环形振荡器及时钟提取电路的瞬态结果.搭制的三级环形振荡器其振荡频率可达400MHz以上,搭制时钟提取电路,提取出的时钟信号可达2Gb/s.     

一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。     

一种CMOS矩形波振荡器设计

振荡器是数字集成电路中常用的单元电路之一,为兼顾振荡频率和CMOS工艺集成,文中从电路结构着手,设计了一种CMOS矩形波振荡器。该振荡器采用标准CMOS电路,能够提供稳定的矩形波信号,信号输出频率和脉宽均可调节。     

A novel high-speed ring oscillator for multiphase clock generationusing negative skewed delay scheme

A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches     

Investigation of a high frequency CMOS unsaturated ring oscillator

Investigation of a high frequency unsaturated ring oscillator with cross coupled load is presented, and oscillation frequency compared with multi-path high frequency ring oscillators. Stability of oscillation is shown heuristically, via geometric argument on a phase plane, where the presence of negative impedance in the cross coupled pair of the delay cell is deemed important. Oscillation frequency formula is presented, and design insight given. In addition, a novel design methodology on lowering its phase noise is developed. Simulations on example circuit designs using 0.18???m CMOS technology demonstrate the higher frequency obtained, oscillation stability, frequency formula and design insight, as well as phase noise methodology.     

多沟道碳纳米晶体管SPICE模型与环形振荡器设计

针对多沟道碳纳米晶体管(MC-CNTFET)越来越接近实用化的发展现状,提出了一种多沟道碳纳米晶体管的集成电路仿真SPICE(Simulation program with integrated ciruit emphasis)模型,并基于此模型,对用多沟道碳纳米晶体管构成的环形振荡器进行了分析.结果表明,该模型能够很...     

A ring oscillator based frequency synthesizer without using frequency divider

A novel indirect frequency synthesizer (FS) circuit comprising a multiplexer (MUX) controlled ring oscillator (RO) and a Hogge phase detector has been proposed. The circuit will synthesize signals having better spectral purity and will consume less power compared to conventional indirect FS circuits. The MUX controlled RO will provide higher flexibility in frequency control and the voltage controlled oscillator (VCO) sensitivity can be varied easily to keep loop gain fixed for different values of synthesized signal frequencies. Hardware experimental results have been given to establish theoretical anticipations.     

Impact of negative bias temperature instability on digital circuit reliability

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.     

Flip-flop resolving time test circuit

Integrated circuit flip-flop resolving time parameters, required for calculation of synchronizer performance and reliability, are measured by wafer probing, without the need for dicing or bonding, by incorporation of test structures on an IC along with the flip-flop to be measured. The circuit has five digital inputs, five digital outputs, including one for frequency measurements, and two analog inputs plus power and ground connections. Several delays that are fabricated as part of the test circuit, including a voltage controlled delay with a few picosecond resolution, are calibrated as part of the test procedure by grating them into and out of the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted, from the period of the ring oscillator with the delay included. A frequency divider is fabricated as part of the test structure to reduce the output of the ring oscillator to less than 200 kHz so no high-frequency inputs of outputs from the IC are required.     

Design of a three-stage ring-type voltage-controlled oscillator with a wide tuning range by controlling the current level in an embedded delay cell

This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage.     

Current amplitude control circuits suitable for current-modeoscillators

A novel current amplitude control circuit suitable for current-mode oscillators is proposed. The circuit is a modified version of the well-known Gilbert gain cell. The technique obtains independent control of oscillation amplitude and small-signal current gain. As an example, the amplitude control circuit is applied to a current-mode oscillator. Simulations were carried out using HSPICE with 0.8 μm Nortel BiCMOS technology and Motorola RF transistors. Simulated results demonstrate that the nonlinear current gain control circuit behaves in a well defined manner. Low distortion and high frequency oscillations are easily obtained when the circuit is applied to a current-mode oscillator     

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24–7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of ?107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40–51 mA from the 1.8-V supply and occupies an area of 440 μm ×  430 μm.     

RTD-HBT高速低功耗环形振荡器的分析

RTD与HBT是高频高速器件,共振隧穿二极管-异质结晶体管(RTD-HBT)环形振荡器有很好的应用前景.详细介绍了RTD-HBT高速低功耗环形振荡器的工作原理,建立了RTD,HBT及RTD-HBT环形振荡器的等效电路模型,并对RTD-HBT环形振荡器用Pspice模拟软件进行了电路模拟.模拟结果与预期结果一致,有助于指导该电路的设计.