High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

DC and microwave performance of a 0.1 μm gate InAs/In0.52Al0.8As MODFET

The authors have measured and analyzed the performance characteristics of 0.1-μm gate InAs/In_0.52Al_0.48 MODFETs grown by molecular beam epitaxy. The transistors are characterized by measured g_m(max)=840 mS/mm, f_T=128 GHz, and a very high current carrying capability, e.g. I_dss=934 mA/mm at V _gs=0.4 V and V_ds=2.7 V. The value of f _T is estimated from extrapolation of the current gain (H ₂₁) at a -6 dB/octave rolloff. This is the first report on the microwave characteristics of an InAs-channel MODFET and establishes the superiority of this heterostructure system     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

Improving the RF performance of 0.18 μm CMOS with deep n-wellimplantation

The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F _t) and maximum oscillation frequency (F_max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F_t and 25% increase in F_max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications     

Positive oxide-charge generation during 0.25 μm PMOSFEThot-carrier degradation

A new hot-carrier degradation mechanism becomes important in 0.25 μm PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge     

0.15 μm T-shaped gate fabrication for GaAs MODFET using phaseshift lithography

A new fabrication process of GaAs MODFETs with 0.15 micron T-shaped gate has been developed by using phase shift lithography. Sub-quarter micron footprints of T-shaped gates are defined as line patterns by PEL (pattern-edge line) method using chemically stable positive photoresist. Parasitic capacitances such as C_gs and C_gd are also reduced by the air-gap incorporated in the present process. An implemented GaAs MODFET exhibited the NF of 0.36 dB and the gain of 11.5 dB at the frequency of 12 GHz     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As pseudomorphic MODFET with high DC and RF performance

AlGaAs/InGaAs MODFETs having 25% indium in the channel and L/sub G/=0.35 mu m have been fabricated. From DC device characterisation, a maximum saturation current of 670 mA/mm and an extrinsic transconductance of 500 mS/mm have been measured. A maximum unilateral gain cutoff frequency of f/sub c/=205 GHz and a maximum current gain cutoff frequency of f/sub T/=86 GHz have been achieved. Bias dependence of f/sub c/ and f/sub T/ has been measured. At 12 GHz a minimum noise figure of NF=0.8 dB and an associated gain of 11 dB have been measured.<>     

Fully integrated 0.25 μm CMOS VCSEL driver with current peaking

A vertical-cavity-surface-emitting laser (VCSEL) driver chip based on a novel circuit concept for current peaking has been designed and fabricated in a 0.25 μm complementary metal-oxide-semiconductor (CMOS) process. This concept allows the easy integration of a peaking driving scheme in CMOS. Experimental results show speed extension from 500 Mbit/s for current on-off to 3.9 Gbit/s for current peaking driving     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

A methodology for deep sub-0.25 μm CMOS technology prediction

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 μm technology and applied to 0.13 μm technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data     

Theory of SiGe waveguide avalanche detectors operating atλ=1.3 μm

The potential performance of SiGe waveguide avalanche photodiodes is analyzed for operation at a wavelength of 1.3 μm. It is found that response speeds in excess of 5 Gbit/s with gains of ~40 should be readily achievable in the absence of carrier trapping effects. Analysis of the electron initiated avalanche current shows an initial low-noise fast pulse due to primary ionization. This is followed by a noisy tail involving hole initiated processes. Structures for future experimental study are proposed     

High performance CW 1.26 μm GaInNAsSb-SQW and 1.20 μmGaInAsSb-SQW ridge lasers

Long-wavelength GaInNAsSb SQW lasers and GaInAsSb SQW lasers that include small amounts of Sb have been successfully grown by gas-source molecular beam epitaxy (GSMBE) and processed into ridge lasers. The GaInNAsSb lasers oscillated under CW operation at 1.258 μm at room temperature. A low CW threshold current of 10.2 mA and high characteristic temperature (T₀) of 146 K were obtained for the GaInNAsSb lasers which is the best result for GaInNAs-based narrow-stripe lasers. Furthermore. The GaInAsSb lasers oscillated under CW operation at 1.20 μm at room temperature. A low CW threshold current of 6.3 mA and high characteristic temperature (T₀) of 756 K were obtained for the GaInAsSb lasers, which is also the best result for the 1.2 μm-range of highly strained GaInAs-based narrow-stripe lasers     

High-speed performance of OMCVD grown InAlAs/InGaAs MSMphotodetectors at 1.5 μm and 1.3 μm wavelengths

A report is presented on the fabrication of high-speed In_0.53 Ga_0.47As metal-semiconductor-metal (MSM) photodetectors incorporating a high-quality lattice-matched InAlAs barrier enhancement layer, grown by organometallic chemical vapor deposition (OMCVD). Fast responses of ~55 ps full-width half-maximum at 1.5 μm and ~48 ps at 1.3 μm wavelengths are observed, corresponding to intrinsic device bandwidths of ~8 GHz and ~11 GHz, respectively. The absence of any tail to the pulse response, and of any low-bias DC gain, indicates a low-trap density at the InAlAs/InGaAs heterointerface. Bias independent dark currents of 10-20 μA are observed below breakdown, which occurred at >30 V in devices with a 500-A-thick InAlAs layer     

An analytical model for self-limiting behavior of hot-carrierdegradation in 0.25 μm n-MOSFET's

Hot-carrier degradation of short-channel n-MOSFETs becomes saturated after reaching a certain threshold value. The physical mechanism for this self-limiting behavior is investigated. It is proposed that the hot-carrier-induced oxide trapped charge and interface states form a potential barrier that repels subsequent hot carriers from causing further damage and can lead to the saturation of device degradation. A physical model is developed on the basis of the analysis. The model is verified by experimental results and can be used for more accurate device reliability projection     

部分耗尽0.25μm SOI射频nMOSFET

结合多项用于深亚微米集成电路的新技术,提出了用于数GHz射频集成电路的SOI nMOSFET器件结构和制造工艺.经过半导体工艺模拟软件Tsuprem4仿真和优化,给出了主要的工艺步骤和详细的工艺条件.制作了0.25μm SOI射频nMOSFET器件,结构和工艺参数同仿真结果一致,测试获得了优良的或可接受的直流及射频性能.     

部分耗尽0.25μm SOI射频nMOSFET

结合多项用于深亚微米集成电路的新技术,提出了用于数GHz射频集成电路的SOI nMOSFET器件结构和制造工艺.经过半导体工艺模拟软件Tsuprem4仿真和优化,给出了主要的工艺步骤和详细的工艺条件.制作了0.25μm SOI射频nMOSFET器件,结构和工艺参数同仿真结果一致,测试获得了优良的或可接受的直流及射频性能.     

High performance sub-0.25 μm devices using ultrathinoxide-nitride-oxide gate dielectric formed with low pressure oxidationand chemical vapor deposition

An ultra-thin, high reliability oxide-nitride-oxide (ONO) gate dielectric was formed using low pressure oxidation and chemical vapor deposition. A sub-0.25 μm device with high performance was fabricated for which the gate dielectric reliability was studied using both Fowler-Nordheim tunneling stress and hot carrier aging. The results from both techniques demonstrate that the device lifetime is longer than 100 years. Auger spectroscopy shows that there is about 9 at.% nitrogen at the SiO₂/Si interface. However, no transconductance degradation is observed     

Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping

The dc and RF characteristics of Si/SiGe n-MODFETs with buried p-well doping incorporated by ion implantation are reported. At a drain-to-source biasV/sub ds/ of +1 V devices with 140-nm gate length had peak transconductance g/sub m/ of 450 mS/mm, and maximum dc voltage gain A/sub v/ of 20. These devices also had "off-state" drain current I/sub off/ of 0.15 mA/mm at V/sub g/=-0.5 V. Control devices without p-well doping had A/sub v/=8.1 and I/sub off/=13 mA/mm under the same bias conditions. MODFETs with p-well doping had f/sub T/ as high as 72 GHz at V/sub ds/=+1.2 V. These devices also achieved f/sub T/ of 30 GHz at a drain current, I/sub d/, of only 9.8 mA/mm, compared to I/sub d/=30 mA/mm for previously published MODFETs with no p-well doping and similar peak f/sub T/.