Data-dependent logic swing internal bus architecture forultralow-power LSI's

A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V     

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits: the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders.     

Silicon single-electron transistors with sidewall depletion gatesand their application to dynamic single-electron transistor logic

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology     

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.     

Statistics of single-electron signals in electron-multiplying charge-coupled devices

Electron-multiplying charge coupled devices promise to revolutionize ultrasensitive optical imaging. The authors present a simple methodology allowing reliable measurement of camera characteristics and statistics of single-electron events, compare the measurements to a simple theoretical model, and report camera performance in a truly photon-counting regime that eliminates the excess noise related to fluctuations of the multiplication gain.     

Fabrication of 3-terminal transferred-electron logic devices by proton bombardment for device isolation

Proton bombardment has been used to convert n GaAs into high-resistivity material. This technique is used for isolating coplanar transferred-electron logic (t.e.l.) devices. The d.c. transfer characteristics of these devices show about 20% current drop. Preliminary experiments indicate that the device propagation delay is of the order of 50 ps.     

Emerging research logic devices

Presents an an assessment of new field-effect transistor, resonant tunnel device, single-electron transistor and quantum cellular automata technologies. The goal of this article is to provide technical assessments of new logic technologies. We attempt to "cast a broad net" to gather in one place alternative concepts for logic that would, if successful, substantially extend the International Technology Roadmap for Semiconductors (ITRS) beyond CMOS. The discussions provide some detail regarding device operation principles, advantages, challenges, maturity, and current and projected performance. The scaling of CMOS device and process technology, as it is known today, is projected to continue (7-nm physical channel length) by 2019. The grand challenge, then, is to invent and develop one or more new technologies that will extend the scaling of information-processing technologies through multiple generations beyond 2019. Such new technologies must meet certain fundamental requirements and possess certain compelling attributes to justify the very substantial investments that are necessary to build a new infrastructure.     

Evaluating programmable logic devices

The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed. It is assumed that the I/O resources of the PLD, which constitute a third axis, are adequate. This allows the analysis to be restricted to an x-y plane fixed along the z-axis. The device's application area, which is the area bounded by its combinational and register capability, is discussed, and methods for calculating the application range are described. Three brief examples demonstrate the ways in which the coordinate system might be used in CAD tools that automate the PLD design process     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

A novel productivity-driven logic element for field-programmable devices

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.     

A comparison of semiconductor devices for high-speed logic

The bipolar transistor and FET are compared, considering both today's most advanced implementations and "ultimate" scaled-down devices. The differences between the devices are quantified in terms of transconductance and intrinsic speed. Old limits are re-examined and ways of extending the devices toward their ultimate in performance are proposed. While the major emphasis is on silicon, a comparison is made with the GaAs MESFET. Other semiconductor devices are discussed in the context of "bipolar-like" and "FET-like" devices, and the HEMT is considered a very promising candidate for high-speed logic. While Josephson junction logic is not discussed at length, it is a continual point of reference. In addition to comparing devices, the on-chip wiring environment is discussed, especially concerning its impact on power-delay products.     

A single-electron half-adder

A single-electron half-adder is presented in this paper. Bits of information are represented by the presence or absence of single electrons at conducting islands. The logic operation of the half-adder is verified using simulation, whereas the stability of its operation is analysed using the Monte Carlo method.     

逻辑器件中的节能技术

近年来,随着采用能降低成本的先进工艺技术,FPGA的应用也日益广泛.但在成本降低的同时,功耗却随着高的晶体管漏电流而增加.     

A novel multiple-valued logic gate using resonant tunneling devices

We demonstrate a novel multiple-valued logic (MVL) gate using series-connected resonant tunneling devices. Logic operation is based on the control of the switching sequence of these devices through the modulation of their peak currents by the input signal. We obtain the literal function, one of fundamental MVL functions, by integrating three InGaAs-based resonant-tunneling diodes with two HEMT's on an InP substrate. The gate configuration is greatly simplified compared with a conventional literal gate employing CMOS circuits     

Design of a Hamming neural network based on single-electron tunneling devices

In this paper, the first complete implementation of a Hamming neural network based on single-electron devices is presented. A large-scale network for character recognition simulation based on building block approach was successfully carried out. Simulations were done using SIMON and MATLAB softwares. Effects such as offset charges and dynamic behavior are taken into account. Moreover, room temperature operation is considered.     

Novel nonresonant optoelectronic logic device

We report the first demonstration of a novel optical logic device having an inverting characteristic which displays hard-limiting and optical gain of more than 10.     

Single-electron logic device with simple structure

A logic gate device is described that can be used to develop single-electron LSIs. The device consists of five capacitors and two tunnelling junctions. It accepts two binary inputs and produces NAND or NOR logic output by making use of the voltage shift in its tunnelling threshold caused by the input signals. Computer simulation of a sample subsystem, or a full adder, consisting of the device demonstrated that it operates correctly.     

Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.     

Statistical modeling of reliability in logic devices

Due to continuous technology scaling VLSI circuits feature an increasing susceptibility to transient faults. While complete elimination of errors cannot be guaranteed, current mitigation techniques based on circuit improvement or architectural measures cause a large overhead in terms of area and energy consumption. A more efficient possibility to cope with transient faults can be to tolerate hardware errors at low physical levels and handle them at higher system levels. This can be achieved by reusing error handling capabilities – such as channel decoders – or introducing specialized error correction blocks that take advantage of the system characteristics by concentrating the effort on the components and bits most crucial for system operation. To enable this approach the influence of hardware errors on system performance needs to be evaluated, requiring spatial and temporal models of error propagation in the system. Since Monte Carlo simulation of complex systems is not feasible, a statistical modeling technique of logic gates and circuits is introduced. This approach allows modeling of noise and variability influences on logic gates as well as correlation due to reconvergent fan-out with an error of 5% compared to Monte Carlo simulation but with considerably less runtime.