Double heterojunction GaAs/GaAlAs I2L inverter

GaAs/GaAlAs double heterojunction I2L inverters with a vertical pnp current source were fabricated by ion implantation and Zn-diffusion into LPE structures. The current gain of the upside-down-operated double heterojunction npn transistor has been improved by a factor of two compared to the gain of the npn transistor of the otherwise similar structure. In addition, the wide-gap junction pnp transistor gives a solution to the critical switch-on problem which can occur when a wide-gap emitter transistor is used for the switching transistor.     

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I–V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I²L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.     

Current hogging injection logic-a new logic with high functional density

A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.     

A complementary DMOS-VMOS IC structure

A new complementary MOS structure has been fabricated consisting of a p-channel DMOS transistor and an n-channel double-diffused VMOS transistor. The transconductance of each transistor was between 0.85-0.98 of the theoretical gm. The threshold voltages have been adjusted by either ion implantation or by adjusting the diffusion profiles. The inverter operation is similar to that of standard CMOS.     

Lateral PNP GaAs bipolar transistor with minimized substrate current

Lateral pnp bipolar transistors have been fabricated using Be implantation to define the emitter and collector areas. The base area (1 - 2 µm wide) has been protected against Be ions during implantation by SiO2and photoresist. The lateral straggling and diffusion during the anneling process reduces the base width, which can be adjusted with the annealing temperature and time. Between the active n-GaAs layer and substrate, a n-Ga0.7Al0.3As layer is deposited. The Be ions penetrating the GaAs/GaAlAs interface form a pn junction in the GaAlAs layer below the emitter and collector area. This reduces the current by several orders of magnitude through the parasitic emitter-substrate (base) diode compared to a GaAs pn junction, due to the higher band gap. For these devices with an effective base width of 0.5 µm, a current gain of 10 in common emitter configuration has been obtained.     

Lateral pnp GaAs bipolar transistor prepared by ion implantation

A lateral pnp bipolar transistor structure has been realised in n-GaAs material using ion implantation. Be ions have been implanted to form the emitter and collector. Proton implantation has been used to reduce the area of the parasitic emitter-substrate diode. First results of a transistor with a current gain of 0.5 are shown.     

Oxide isolated ISL technologies

Using oxide isolation, ISL gates can be fabricated without the relative slow lateral pnp transistor which is inevitable in pn-isolated processes. Now the clamping action is provided either by a fast vertical pnp only, or a reverse operated npn. Using a 1.2 µm thick epilayer and 3 µm minimum dimensions, propagation delay times of 0.7 ns are obtained at a current level of 200 µA per gate.     

Oxygen implantation to suppress parasitic bipolar action in CMOS

Oxygen implantation and subsequent epitaxial silicon deposition have been developed to improve CMOS latchup prevention through reducing the current gains of parasitic bipolar transistors. The buried oxygen implanted layer is well confined, and defects do not extend into the epitaxial silicon layer. The device characteristics of the n- and p-MOSFETs fabricated on a wafer with the oxygen implantation are therefore not affected by the buried implanted layer. The oxygen implanted layer can reduce the minority-carrier lifetime and hence decrease the current gain of the lateral parasitic bipolar transistor. In addition, it introduces a potential barrier which decreases the current collected at the frontside contact of the vertical parasitic bipolar transistor. The common base current gain is reduced by 50% and 80% for the lateral and the vertical parasitic bipolar transistors, respectively. As a consequence, the CMOS latchup immunity is significantly improved     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

新型I~2L电路的试验研究

为了提高I~2L电路的速度,本文利用新型器件——四极并合晶体管代替pnp管进行电流注入,结果表明,在相同注入极电压下,I~2L电路的速度有较明显提高.同时,仍保持工艺简单、适于集成等优点.     

Triple implant (In,Ga)As/InP n-p-n heterojunction bipolar transistors for integrated circuit applications

For the first time (In,Ga)As/InP n-p-n heterojunction bipolar transistors (HJBT's) applicable to integrated circuits have been fabricated by triple ion implantation. The base has been formed by beryllium ion implantation and the collector by silicon ion implantation. The implants were made into an LPE-grown n-n (In,Ga)As/InP heterostructure on an n+-InP substrate. This inverted mode emitter-down heterojunction transistor structure demonstrates to a maximum current gain of 7 with no hysteresis in the characteristics. The ideality factors of the IBversus VBE, and ICversus VBEcharacterisitics with VCB= 0, are 1.25 and 1.08, respectively, indicating that the defect level in the herterojunction is low and that minority-carrier injection and diffusion is the dominant current flow mechanism.     

A SPICE compatible subcircuit model for lateral bipolar transistorsin a CMOS process

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 μm CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJT's)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction     

AlGaAs/GaAs emitter-down HBT fabricated by MBE overgrowth

A planar emitter-down AlGaAs/GaAs heterojunction bipolar transistor (HBT) has been fabricated by a molecular beam epitaxy overgrowth of the n-GaAs collector on top of the base layer after the base layer was formed by beryllium implantation and rapid thermal annealing. The emitter down transistors fabricated by this process had DC current gains of 20, and ring oscillators gave a maximum switching speed of 250 ps/gate.<>     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

Vertical bipolar transistors on buried silicon nitride layers

The letter reports on the integration of vertically operating n-p-n-bipolar transistors with base widths of about 1 µm in silicon-on-insulator (SOI) structures. Nitrogen ion implantation at substrate temperatures of 550°C and subsequent SiCl4epitaxy provide SOI films with excellent crystalline quality. Conventional bipolar diffusion processes have been applied in order to fabricate diodes and vertical bipolar transistor arrays on thus isolated epitaxial layers. The leakage current of SOI diodes exceeds the value for bulk devices only by a factor of 2. The transistors exhibit emitter current gains of up to 100 and emitter-collector breakdown voltages of up to 35 V.     

Fabrication of widegap-emitter Schottky-collector transistor using GaInAs/InP

A widegap-emitter transistor with a Schottky collector has been fabricated using n-InP as the emitter, p-GaInAs as the base layer and Ni as the Schottky metallisation. The fabricated transistors show a current gain better than 5 in the common-emitter configuration.     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

Fully Radiative Current Path Structure (FRACS) for sub-0.1 μmemitter transistor

A new structure is proposed for bipolar transistors - FRACS (Fully Radiative Current Path Structure). A FRACS transistor has a line emitter and a cylindrical base and collector or a point emitter and a spherical base and collector. Device parameters of the FRACS transistor is obtained by extending the conventional one-dimensional transistor model to a two- or three-dimensional model. In this structure, base transit time is reduced as the emitter size is reduced by radiative collector current flow. Using this model, a general bipolar transistor with a shallow link base is found to increase the cutoff frequency as the emitter size is reduced. The Kirk effect is suppressed in this structure because of the small collector current density at the collector-base junction. The effect was experimentally examined. A cylindrical base was fabricated by thermal diffusion of boron to achieve the FRACS transistor. Cutoff frequency was observed to increase as the emitter size was reduced. Maximum cut-off frequency of 64 GHz was achieved by this transistor with a 25-nm thick base formed by rapid vapor-phase diffusion     

The benefits of fluorine in pnp polysilicon emitter bipolartransistors

BF₂ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF₂ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior     

Gamma radiation effects on integrated injection logic cells

Integrated injection-logic (I²L) cells were tested to determine their characteristics after exposure to a total dose gamma-radiation environment. These particular devices were not designed or fabricated with radiation hardness as a goal. The common-base current gain of the lateral p-n-p transistor, the common-emitter current gain of the vertical n-p-n transistor and the forward current-voltage characteristics of the injector-substrate junction were measured over the current range of 100 nA to 300 µA as a function of dose. In addition, the propagation delay time versus power dissipation per gate at various dose levels was determined from frequency of oscillation measurements of a multiple inverter circuit.