FPGA based acceleration and deceleration circuit for industrial robots and CNC machine tools

In order to make industrial robots and computer numerical control (CNC) machine tools perform tasks efficiently, many techniques for the acceleration and deceleration of industrial robots and CNC machine tools have been proposed. Polynomial technique can generate velocity profiles of various acceleration and deceleration characteristics, but it requires a lot of computations. Digital convolution technique can generate efficiently velocity profiles, but it cannot generate velocity profiles with some kinds of acceleration and deceleration characteristics. This paper proposes an efficient approach for generating velocity profiles that cannot be generated by previous techniques as well as velocity profiles generated by them. Based on the proposed approach, an acceleration and deceleration circuit for industrial robots and CNC machine tools is designed by using the VHDL and it is implemented with a FPGA. A velocity profile generated by the acceleration and deceleration circuit will be applied to one single-axis control system.     

Model development

In 2001, the Object Management Group (OMG), an IT industry standards body, came up with the Model Driven Architecture (MDA), an approach to software development grounded on the principles of high-level abstraction and hardware independence. Using MDA, teams of developers, it was proposed, would build a model of their system, which would then be used to create not just working prototypes but almost all the software code of the finished application. In its current version, 1.5, UML lacks the full functionality needed to realise the MDA ideal. The next release, UML 2, is intended to overcome the deficiencies of UML 1.5, adding features to fully support MDA and allow tools to generate working software code from UML models in a standard way.     

基于FPGA的移动通信中卷积码编码器设计

卷积码是一种性能优良的差错控制编码。介绍了卷积码编码原理,基于FPGA利用VHDL硬件描述语言实现了一个（2,1,9）卷积码编码器。给出了仿真结果,并在FPGA器件上验证实现。仿真及测试结果表明,达到了预期的设计要求,并用于实际项目中。     

基于FPGA的高速采样单元实现

介绍了一种基于FPGA的高速采样单元硬件实现,包括数据采集器周边电路设计、高速数据传输方法和设计要点、运算处理单元设计、总线控制设计和VHDL程序编写框架。将信号进行样式转换,由采样器转换并通过可编程门阵列FPGA进行处理并存储,再由系统进行控制完成整个采样单元的数据传输。     

基于FPGA 的 ARINC429 总结接收发送系统的设计

根据ARINC429总线数据输入标准的要求,提出了一种基于FPGA的透明数据传输系统方案。该方案实现四路ARINC429信号接收,两路ARINC429信号发送的功能。重点研究接收发送系统的硬件电路设计和使用VHDL语言的软件开发,并给出部分VHDL语言描述。经验证,该方案能较好地满足ARINC429通信系统的要求。     

基于UML的面向对象建模方法的研究

为了研究较好的软件建模方法,运用UML中的5种图对面向对象建模的方法进行讨论及技术研究,提出如下建模过程：首先是系统需求;随后分析问题领域,建立系统的用例图;接着,建立系统的静态结构模型,并将系统的功能需求分解到各个对象类,以确定各个对象类的责任;然后,建立系统的动态行为模型;最后,给出物理模型。通过实例,对UML的面向对象建模机制做了系统概述,表明UML是一种优秀的建模语言,使用UML有助于开发者对整个系统有清晰的认识,从而建立各种系统模型,为后期编码工作做好充分的前期准备。     

CDMA2000系统中前向链路卷积编码器的FPGA实现

为了缩短卷积编码器设计周期,使硬件设计更具灵活性,在介绍卷积编码器原理的基础上,论述了一种基于可编程逻辑器件,采用模块化设计方法,利用VHDL硬件描述语言实现CDMA2000系统前向链路卷积编码器的方法,给出了在QuartusⅡ软件下的仿真结果,并在FPGA器件上验证实现。仿真和实验都证明了这种方法的可行性和正确性。     

Hardware design implementation issues of the estimator-based controller using FPGA

Hardware implementation issues play a vital role to realize the system accurately. Realization of hardware in digital domain has more advantages than analog domain. Field programming gate array (FPGA) based architectures are suitable for fast and reconfigurable systems. In this paper, implementation issues of an estimator based controller using FPGA are discussed. Verilog coding is developed to defeat these issues and efficient hardware mapping is derived. Input signal processing is proposed to overcome the analog to digital converter (ADC) interfacing issues such as quantization, sampling rate, resolution, non-linearity error and offset error. Optimum bit sizing of digital control modules are derived, considering system requirements and specifications. Controller operations are analyzed in binary form to choose the bit size of various operands and control modules, to derive accurate results. In this application, a 16-bit control architecture is proposed to estimate states of the converter and to generate control signals. Estimator based controller is designed for a dc-dc converter. Atlys Spartan-6 XC6SLX45 FPGA is used to implement the controller. Implementation issues such as ADC errors, settling time, the bit size of variables, quantization effects of the estimator and controller are mainly focused. It enables verilog coding quite easier to implement non-linear controllers using FPGA.     

Efficient test case generation for validation of UML activity diagrams

Unified Modeling Language (UML) is widely used as a system level specification language in embedded system design. Due to the increasing complexity of embedded systems, the analysis and validation of UML specifications is becoming a challenge. UML activity diagram is promising to modeling the overall system behavior. However, lack of techniques for automated test case generation is one major bottleneck in the UML activity diagram validation. This article presents a methodology for automatically generating test cases based on various model checking techniques. It makes three primary contributions: First, we propose coverage-driven mapping rules that can automatically translate activity diagram to formal models. Next, we present a procedure for automatic property generation according to error models. Finally, we apply various model checking based test case generation techniques to enable efficient test case generation. Our experimental results demonstrate that our approach can reduce the validation effort drastically by reducing both test case generation time and required number of test cases to achieve a functional coverage goal.     

一个基于UML协作图的集成测试用例生成方法

UML协作图描述了系统的一个协作过程中参与对象之间的结构关系和交互行为,确认它们是否被正确实现是集成测试的工作.本文提出了一个基于UML协作图生成集成测试用例的方法,将表示设计的协作图作为测试模型,首先通过遍历每条消息的直接后继识别协作图中的表示用例实现的所有可能的场景路径,然后在遍历每条场景路径的过程中获取相应协作执行的路径条件、参数变量和预期方法调用序列,最后使用范畴-划分方法确定场景路径上的输入、输出、环境条件的合理组合作为覆盖该场景路径的测试用例,用于测试一个协作场景路径上的交互行为.该方法,集成了白盒方法和黑盒方法,在覆盖所有的测试需求的前提下,生成的测试用例较少.     

1024QAM调制解调系统的FPGA实现

在MQAM调制解调原理的基础上重点介绍了如何利用DSP Builder实现1024QAM调制解调系统模型以及对模型进行算法级仿真和生成VHDL代码,以及与第三方软件结合生成的VHDL代码如何下载到FPGA器件中进行验证.     

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word-length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC.     

快速实现基于FPGA的脉动FIR滤波器

基于FPGA(现场可编程门阵列)器件内部集成的数字信号处理模块,利用QuartusⅡ中宏功能模块定制4阶卷积运算单元,利用VHDL(甚高速集成电路硬件描述语言)元件例化语句生成脉动阵列结构FIR(有限冲击响应)滤波器。研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。与已有的实现方法相比,文中提出的方法具有更短的设计周期、更强的可移植性、更高的工作频率和实时处理信号的能力。     

Design and verification of SystemC transaction-level models

Transaction-level modeling allows exploring several SoC design architectures, leading to better performance and easier verification of the final product. In this paper, we present an approach to design and verify SystemC models at the transaction level. We integrate the verification as part of the design flow where we first model both the design and the properties (written in Property Specification language) in Unifed Modeling Language (UML); then, we translate them into an intermediate format modeled with AsmL [language based on Abstract State Machines (ASM)]. The AsmL model is used to generate a finite state machine of the design, including the properties. Checking the correctness of the properties is performed on the fly while generating the state machine. Finally, we translate the verified design to SystemC and map the properties to a set of assertions (as monitors in C#) that can be reused to validate the design at lower levels by simulation. For existing SystemC designs, we propose to translate the code back to AsmL in order to apply the same verification approach. At the SystemC level, we also present a genetic algorithm to enhance the assertions coverage. We will ensure the soundness of our approach by proving the correctness of the SystemC-to-AsmL and AsmL-to-SystemC transformations. We illustrate our approach on two case studies including the PCI bus standard and a master/slave generic architecture from the SystemC library.