Silicon p-FETs from ultrahigh density nanowire arrays

Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 10(18) cm-3. Top-gated 4-microm-wide Si nanowire p-FETs yielded low off-currents (approximately 10(-12) A), high on/off ratios (10(5)-10(6)), good on current values (30 microA/microm), high mobilities (approximately 100 cm2/V-s), and low subthreshold swing values (approximately 80 mV/decade between 10(-12) and 10(-10) A increasing to 200 mV/decade between 10(-10)-10(-8) A).     

Experimental study on the subthreshold swing of silicon nanowire transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.     

Preparation and electrical properties of electrospun tin-doped indium oxide nanowires

Well-aligned tin-doped indium (ITO) nanowires have been prepared using the electrospinning process. The Sn doping mechanism and microstructure have been characterized by x-ray diffraction (XRD) and x-ray photoelectron spectroscopy (XPS). Devices for I-V measurement and field-effect transistors (FETs) were assembled using ITO nanowires with top contact configurations. The effect of Sn doping on the electrical conductivity was significant in that it enhanced the conductance by over 10(7) times, up to ～1?S?cm(-1) for ITO nanowires with an Sn content of 17.5 at.%. The nanowire FETs were operated in the depletion mode with an electron mobility of up to 0.45?cm(2)?V(-1)?s(-1) and an on/off ratio of 10(3).     

Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Multi-quantum-well nanowire heterostructures for wavelength-controlled lasers

Rational design and synthesis of nanowires with increasingly complex structures can yield enhanced and/or novel electronic and photonic functions. For example, Ge/Si core/shell nanowires have exhibited substantially higher performance as field-effect transistors and low-temperature quantum devices compared with homogeneous materials, and nano-roughened Si nanowires were recently shown to have an unusually high thermoelectric figure of merit. Here, we report the first multi-quantum-well (MQW) core/shell nanowire heterostructures based on well-defined III-nitride materials that enable lasing over a broad range of wavelengths at room temperature. Transmission electron microscopy studies show that the triangular GaN nanowire cores enable epitaxial and dislocation-free growth of highly uniform (InGaN/GaN)n quantum wells with n=3, 13 and 26 and InGaN well thicknesses of 1-3 nm. Optical excitation of individual MQW nanowire structures yielded lasing with InGaN quantum-well composition-dependent emission from 365 to 494 nm, and threshold dependent on quantum well number, n. Our work demonstrates a new level of complexity in nanowire structures, which potentially can yield free-standing injection nanolasers.     

Electrical properties of 10-nm-radius n-type gate all around twin Si nanowire field effect transistors

The electrical properties of 10-nm-radius n-type gate all around (GAA) twin Si nanowire field effect transistors (TSNWFETs) and field effect transistors (FETs) without nanowires were investigated to understand their device characteristics. The electrical characteristics of the GAA TSNWFETs and FETs with bulk boron concentrations of 1 x 10(18) and 1 x 10(16) cm(-3) were simulated by using three-dimensional technology computer-aided design simulation tools of sentaurus taking into account quantum effects. The simulation results showed that the on-current level of the TSNWFETs was larger than that of FETs, and the subthreshold swing and the drain induced barrier lowing of the TSNWFETs were smaller than those of FETs. The current density and conduction band edge profiles in the TSNWFETs clarified the dominant current paths. The simulation results showed that the on-current/off-current ratio increased with increasing bulk boron concentration, and the stand-by current level decreased.     

Doping of Si into GaN nanowires and optical properties of resulting composites

Doping of Si into GaN nanowires has been successfully attained via thermal evaporation in the presence of a suitable gas atmosphere. Analysis indicated that the Si-doped GaN nanowire is a single crystal with a hexagonal wurtzite structure, containing 2.2 atom % of Si. The broadening and the shift of Raman peak to lower frequency are observed, which may be attributed to surface disorder and various strengths of the stress. The band-gap emission (358 nm) of Si-doped GaN nanowires relative to that (370 nm) of GaN nanowires has an apparent blue shift (approximately 12 nm), which can be ascribed to doping impurity Si.     

Fabrication of large number density platinum nanowire arrays by size reduction lithography and nanoimprint lithography

Large number density Pt nanowires with typical dimensions of 12 microm x 20 nm x 5 nm (length x width x height) are fabricated on planar oxide supports. First sub-20 nm single crystalline silicon nanowires are fabricated by size reduction lithography, and then the Si nanowire pattern is replicated to produce a large number of Pt nanowires by nanoimprint lithography. The width and height of the Pt nanowires are uniform and are controlled with nanometer precision. The nanowire number density is 4 x 10(4) cm(-1), resulting in a Pt surface area larger than 2 cm(2) on a 5 x 5 cm(2) oxide substrate. Bimodal nanowires with different width have been generated by using a Pt shadow deposition technique. Using this technique, alternating 10 and 19 nm wide nanowires are produced.     

Nanowire lithography: fabricating controllable electrode gaps using Au-Ag-Au nanowires

A method to fabricate nanowire electrodes possessing controllable gaps is described. The method relies on electrochemical deposition and selective chemical etching or heating to selectively remove the Ag segment of Au-Ag-Au nanowires. Because the thickness of the Ag segment directly dictates the size of the nanogap, the gap width can be easily controlled during the nanowire fabrication process. Herein, we demonstrate gaps with 2 microm, 100 nm and 20 nm widths via the above-mentioned approaches. In addition, we observed that small gaps (approximately 20 nm) can be formed through annealing Au-Ag-Au nanowires at 200 degrees C in air. Electrical contact between nanowire electrodes and contact pads is studied. Using nanowire electrodes with a 100 nm gap, we subsequently fabricate organic field effect transistors (FETs) with regioregular poly(3-hexylthiophene).     

Mobility Deception in Nanoscale Transistors: An Untold Contact Story

Mobility is a critical parameter that is routinely used for benchmarking the performance of field‐effect transistors (FETs) based on novel nanomaterials. In fact, mobility values are often used to champion nanomaterials since high‐performance devices necessitate high mobility values. The current belief is that the contacts can only limit the FET performance and hence the extracted mobility is an underestimation of the true channel mobility. However, here, such misconception is challenged through rigorous experimental effort, backed by numerical simulations, to demonstrate that overestimation of mobility occurs in commonly used geometries and in nanomaterials for which the contact interface, contact doping, and contact geometry play a pivotal role. In particular, dual‐gated FETs based on multilayer MoS₂ and WSe₂ are used as case studies in order to elucidate and differentiate between intrinsic and extrinsic contact effects manifesting in the mobility extraction. The choice of 2D layered transition metal dichalcogenides (TMDCs) as the semiconducting channel is motivated by their potential to replace and/or coexist with Si‐based aging FET technologies. However, the results are equally applicable to nanotube‐ and nanowire‐based FETs, oxide semiconductors, and organic‐material‐based thin‐film FETs.     

Development of ultra-high density silicon nanowire arrays for electronics applications

This article reviews our recent progress on ultra-high density nanowires (NWs) array-based electronics. The superlattice nanowire pattern transfer (SNAP) method is utilized to produce aligned, ultra-high density Si NW arrays. We fi rst cover processing and materials issues related to achieving bulk-like conductivity characteristics from 10 20 nm wide Si NWs. We then discuss Si NW-based fi eld-effect transistors (FETs). These NWs & NW FETs provide terrifi c building blocks for various electronic circuits with applications to memory, energy conversion, fundamental physics, logic, and others. We focus our discussion on complementary symmetry NW logic circuitry, since that provides the most demanding metrics for guiding nanofabrication. Issues such as controlling the density and spatial distribution of both p-and n-type dopants within NW arrays are discussed, as are general methods for achieving Ohmic contacts to both p-and n-type NWs. These various materials and nanofabrication advances are brought together to demonstrate energy effi cient, complementary symmetry NW logic circuits.     

Ultra-sharp pointed tip Si nanowires produced by very high frequency plasma enhanced chemical vapor deposition via VLS mechanism

Needle-like silicon nanowires have been grown using gold colloid as the catalyst and silane (SiH₄) as the precursor by very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD). Si nanowires produced by this method were unique with sharpness below 3 nm. High resolution transmission electron microscopy (HRTEM) and X-ray diffraction technique (XRD) confirmed the single crystalline growth of the Si nanowires with (111) crystalline structure. Raman spectroscopy also has revealed the presence of crystalline Si in the grown Si nanowire body. In this research, presence of a gold nanoparticle on tip of the nanowires proved vapor–liquid–solid growth mechanism.     

Single wire radial junction photovoltaic devices fabricated using aluminum catalyzed silicon nanowires

Single nanowire radial junction solar cell devices were fabricated using Si nanowires synthesized by Al-catalyzed vapor-liquid-solid growth of the p(+) core (Al auto-doping) and thin film deposition of the n(+)-shell at temperatures below 650 °C. Short circuit current densities of 11.7 mA cm(-2) were measured under 1-sun AM1.5G illumination, showing enhanced optical absorption. The power conversion efficiencies were limited to < 1% by the low open circuit voltage and fill factor of the devices, which was attributed to junction shunt leakage promoted by the high p(+)/n(+) doping. This demonstration of a radial junction device represents an important advance in the use of Al-catalyzed Si nanowire growth for low cost photovoltaics.     

Interface charge induced p-type characteristics of aligned Si(1-x)Gex nanowires

This study reports the electrical transport characteristics of Si(1-x)Gex (x=0-0.3) nanowires. Nanowires with diameters of 50-100 nm were grown on Si substrates. The valence band spectra from the nanowires indicate that energy band gap modulation is readily achievable using the Ge content. The structural characterization showed that the native oxide of the Si(1-x)Gex nanowires was dominated by SiO2; however, the interfaces between the nanowire and the SiO2 layer consisted of a mixture of Si and Ge oxides. The electrical characterization of a nanowire field effect transistor showed p-type behavior in all Si(1-x)Gex compositions due to the Ge-O and Si-O-Ge bonds at the interface and, accordingly, the accumulation of holes in the level filled with electrons. The interfacial bonds also dominate the mobility and on- and off-current ratio. The large interfacial area of the nanowire, together with the trapped negative interface charge, creates an appearance of p-type characteristics in the Si(1-x)Gex alloy system. Surface or interface structural control, as well as compositional modulation, would be critical in realizing high-performance Si(1-x)Gex nanowire devices.     

Dramatically enhanced ultraviolet photosensing mechanism in a n-ZnO nanowires/i-MgO/n-Si structure with highly dense nanowires and ultrathin MgO layers

This study reports that the visible-blind ultraviolet (UV) photodetecting properties of ZnO nanowire based photodetectors were remarkably improved by introducing ultrathin insulating MgO layers between the ZnO nanowires and Si substrates. All layers were grown without pause by metal organic chemical vapor deposition and the density and vertical arrangement of the ZnO nanowires were strongly dependent on the thickness of the MgO layers. The sample in which an MgO layer with a thickness of 8 nm was inserted had high density nanowires with a vertical alignment and showed dramatically improved UV photosensing performance (photo-to-dark current ratio = 1344.5 and recovery time = 350 ms). The photoresponse spectrum revealed good visible-blind UV detectivity with a sharp cut off at 378 nm and a high UV/visible rejection ratio. A detailed discussion regarding the developed UV photosensing mechanism from the introduction of the i-MgO layers and highly dense nanowires in the n-ZnO nanowires/i-MgO/n-Si substrates structure is presented in this work.     

Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.     

Controlled synthesis of millimeter-long silicon nanowires with uniform electronic properties

We report the nanocluster-catalyzed growth of ultralong and highly uniform single-crystalline silicon nanowires (SiNWs) with millimeter-scale lengths and aspect ratios up to approximately 100 000. The average SiNW growth rate using disilane (Si 2H 6) at 400 degrees C was 31 mum/min, while the growth rate determined for silane (SiH 4) reactant under similar growth conditions was 130 times lower. Transmission electron microscopy studies of millimeter-long SiNWs with diameters of 20-80 nm show that the nanowires grow preferentially along the 110 direction independent of diameter. In addition, ultralong SiNWs were used as building blocks to fabricate one-dimensional arrays of field-effect transistors (FETs) consisting of approximately 100 independent devices per nanowire. Significantly, electrical transport measurements demonstrated that the millimeter-long SiNWs had uniform electrical properties along the entire length of wires, and each device can behave as a reliable FET with an on-state current, threshold voltage, and transconductance values (average +/-1 standard deviation) of 1.8 +/- 0.3 muA, 6.0 +/- 1.1 V, 210 +/- 60 nS, respectively. Electronically uniform millimeter-long SiNWs were also functionalized with monoclonal antibody receptors and used to demonstrate multiplexed detection of cancer marker proteins with a single nanowire. The synthesis of structurally and electronically uniform ultralong SiNWs may open up new opportunities for integrated nanoelectronics and could serve as unique building blocks linking integrated structures from the nanometer through millimeter length scales.     

Porosity control in metal-assisted chemical etching of degenerately doped silicon nanowires

We report the fabrication of degenerately doped silicon (Si) nanowires of different aspect ratios using a simple, low-cost and effective technique that involves metal-assisted chemical etching (MacEtch) combined with soft lithography or thermal dewetting metal patterning. We demonstrate sub-micron diameter Si nanowire arrays with aspect ratios as high as 180:1, and present the challenges in producing solid nanowires using MacEtch as the doping level increases in both p- and n-type Si. We report a systematic reduction in the porosity of these nanowires by adjusting the etching solution composition and temperature. We found that the porosity decreases from top to bottom along the axial direction and increases with etching time. With a MacEtch solution that has a high [HF]:[H(2)O(2)] ratio and low temperature, it is possible to form completely solid nanowires with aspect ratios of less than approximately 10:1. However, further etching to produce longer wires renders the top portion of the nanowires porous.     

Ultralong zinc-blende ZnS nanowires grown on polar C face of 6H-SiC substrates at low temperatures by metalorganic chemical vapor deposition

Ultralong ZnS nanowires with high purity were grown on Au-coated polar C face of 6H-SiC substrates via metalorganic chemical vapor deposition at low temperatures. The ZnS nanowires have zinc-blende structure and the length is up to tens of micrometers. HRTEM investigations show that the nanowires are well crystalline single crystal grown along [1 1 1] and free of bulk defects. However, sparse straight and curved nanowires with poor crystalline nature are randomly grown on the Au-coated Si face of 6H-SiC substrates. We deduce that the growth of ZnS is related to the substrates and C face can enhance Au-catalytic VLS growth. The CL spectra of an individual nanowire grown on C and Si face reveal different optical properties. Intrinsic sulfur and zinc vacancies are the main reasons for the 458.1 nm and 459.2 nm blue emission detected in the nanowire grown on C face and Si face, respectively. Nevertheless, an unusual green emission at 565.1 nm is observed in the poor crystalline nanowire grown on Si face, which originates from the bulk defects.