一种新的高性能开关电容排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

MPEG2视频解码器VLSI结构研究

介绍了ＭＰＥＧ２视频解码器的ＶＬＳＩ实现方法，采用ＡＳＩＣ结构实现ＭＰＥＧ２标准的视频解码，用流水线哈佛结构ＲＩＳＣ型微控制器对视频数据流、变字长解码以及电路时序进行控制，提高了电路速度，减小了芯片面积。     

一种新的高性能开关电流排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

自对准硅化物SOI／CMOS技术研究

在ＳＯＩ／ＣＭＯＳ电路制作中引入了自对准钴硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩ／ＭＯＳＦＥＴ单管特性和ＳＯＩ／ＣＭＯＳ电路速度性能的影响。实验表明，ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和薄层电阻，改善单管的输出特性，降低ＳＯＩ／ＣＭＯＳ环振电路门延迟时间，提高ＳＯＩ／ＣＭＯＳ电路的速度特性。     

自对准硅化物CMOS／SOI技术研究

在ＣＭＯＳ／ＳＩＭＯＸＳＯＩ电路制作中引入了自对准钴（Ｃｏ）硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩＭＯＳＦＥＴ单管特性和ＣＭＯＳ／ＳＯＩ电路速度性能的影响．实验表明，采用ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和方块电阻，改善单管的输出特性，降低ＣＭＯＳ／ＳＯＩ环振电路门延迟时间，提高ＣＭＯＳ／ＳＯＩ电路的速度特性．     

ISO／IEC MPEG—2先进音频编码（一）

在对兼容性没有任何要求的条件下，ＩＳＯ／ＩＥＣＭＰＥＧ－２先进音频编码（ＡＡＣ）系统使ＩＳＯ／ＩＥＣＭＰＧＥ－２编码具有最好的音频质量，叙述了ＡＡＣ系统（ＩＳＯ／ＩＥＣ１３８１８－７）的主要特点，ＭＰＥＧ－２ＡＡＣ把高分辨率滤波器组，预测技术，霍夫曼编码的编码效率和其他功能结合在一起，可以在数据率可变的情况下，传输品质极高的音频。     

智翔推出LS3016A交换机

智翔 (ＬＡＮＴＥＣＨ)公司推出的ＬＳ３０１６Ａ和ＬＳ３０１６ＡＰｌｕｓ是两款高性价比的１６口１０／１００Ｍｂｉｔ／ｓ快速以太网交换机 ,支持ＩＥＥＥ８０２．３、８０２．３ｕ、８０２．３ｘ、ＩＥＥＥ８０２．１Ｑ及ＩＥＥＥ８０２．１ｑ等标准。该产品具有自动线序识别 (识别直联线、交叉线 )功能 ,紧凑小巧的设计为桌面及ＳＯＨＯ应用节省了所占的空间。ＬＳ３０１６ＡＰｌｕｓ具有３种类型的ＱｏＳ功能 (Ｐｏｒｔ-ｂａｓｅｄ、ＶＬＡＮｔａｇ、ＴｏＳ／ＤＳ) ,可以很好地支持多媒体应用及实时的网络应用 ,在防止包延迟的同时无…     

IBND推出为宽带服务的PIC高性能双绞线分布电缆

日前,ＩＢＤＮ向布线业界推出了高性能双绞线ＰＩＣ分布电缆。ＩＢＤＮ的高性能双绞线电缆与服务线缆完全符合并超过了ＴＩＡ／ＥＩＡ－５６８Ａ和ＣＳＡＴ５２９－９５五类性能规范,为园区环境内局域网的互配连接提供一种经济的解决方案。ＩＢＤＮ高性能双绞线ＰＩＣ分布电缆可以配备为ＡＤＳＬ、ＨＤＳＬ或ＶＤＳＬ调制解调器技术传输宽带信号的布线系统。该电缆在高频下的优良传输性能使其在采用ＶＤＳＬ调制解调器时,数据传输率在１０００米传输距离上达到５２Ｍｂ／ｓ或在１５００米传输距离上达到２６Ｍｂ／ｓ。该电缆具备的优越…     

国产操作系统COSIX和国产系统软件平台COSA

介绍了国产操作系统ＣＯＳＩＸＶ１．２和ＣＯＳＩＸＶ．２０国产系统软件平台ＣＯＳＡＶ１．０。ＣＯＳＡＶ１．０由国产操作系统ＣＯＳＩＸＶ１．２，国产网络系统ＣＯＮＥＴＶ１．０，国产数据库管理系统ＣＯＢＡＳＥＶ１．０以及国产编程软件Ｃ、Ｃ＋＋、ＦＧｏｒｔｒａｎ９０等构成。ＣＯＳＩＸＶ１．２遵循国际法标准ＰＯＳＩＸ．１、工业标准ＸＰＧ３，与主流ＵＮＩＸ系统ＳＶＲ４二进制兼容。ＣＯＳＩＸＶ２．０是基于微内核     

利用电子束掺杂技术制备微米、亚微米P－MOSFET器件

本文对辉光放电电子束在ＭＯＳＦＥＴ中的应用进行研究．结果表明，利用辉光放电电子束掺杂方法成功地实现了微米、亚微米Ｐ－ＭＯＳＰＥＴ．器件的漏流小，Ｉ－Ｖ特性好，源漏结浅、均匀和横向掺杂效应小．此方法与常规ＭＯＳ工艺兼容，所需的设备结构简单、操作方便，价格低廉，易于推广到ＶＬＳＩ中去．     

一种全搜索低功耗运动估计IP核的设计

根据全搜索块匹配算法,提出了一种解析度可调的高效低功耗运动估计IP核结构.该结构用于处理8×8宏块并且搜索区域为[-7,7].设计采用了蛇形寄存器组和二维脉动阵列结构,在提高计算速度的同时极大的减少了输入数据带宽.设计采用低功耗设计技术大幅减低了电路的功耗.IP核在FPGA上验证通过,该电路的工作频率在80 MHz的时候就可以满足帧率为25 frame/s和帧尺寸为720×576的视频序列的实时压缩处理要求.     

A modularized processor LSI with a highly parallel structure forcontinuous speech recognition

A speech recognition processor CMOS LSI was developed as the processing element (PE) of a ring array processor previously proposed by the authors as architecture to carry out highly parallel recognition processing with array size flexibility. There are three key features for the LSI: (1) a highly parallel I/O structure of triple buffer with cyclical-mode transition control methods to solve the serious problem of inter-PE data transfer overhead versus the array processing; (2) a control structure with two direct memory access (DMA) controllers to realize inter-PE data I/O processing and intra-PE processing in parallel; and (3) a pipelined recognition processing at a high execution rate realized by a pipelined structure and a balanced clock distribution design technique. These effective designs for the PE LSI allow high-speed recognition processing without any inter-PE data transfer overhead in the ring array processor. Combining the PE-LSI architecture with the proposed array architecture for highly parallel dynamic time warping (DTW) processing, a real-time continuous speech recognition system based on continuous dynamic programming matching using the SPLIT method for a 1000-word vocabulary, can be constructed using a ring array processor consisting of 30 PEs     

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs     

System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs

A VLSI architecture for the block matching motion estimation is described in this paper. The proposed architecture achieves 100% PE utilization and alleviates I/O bottleneck problem using small amount of distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirement. The overall computations are performed in pipelined manner and the data fill time for contiguous block is eliminated to increase throughput. The VLSI system implementation methodologies and the layouts are also described. Finally, the performances are evaluated and the advantages are outlined, compared to other architectures.     

High Throughput,Scalable VLSI Architecture for Block Matching Motion Estimation

A VLSI architecture for the block matching motion estimation is described in this paper. The proposed architecture achieves 100% PE utilization and alleviates I/O bottleneck problem using small amount of distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirement. The overall computations are performed in pipelined manner and the data fill time for contiguous block is eliminated to increase throughput. The VLSI system implementation methodologies and the layouts are also described. Finally, the performances are evaluated and the advantages are outlined, compared to other architectures.     

基于GEA运动估计算法的低功耗容错VLSI结构

提出了一种能量高效的运动估计结构.该结构基于GEA (Global Elimination Algorithm)算法,在并行GEA结构的基础上,对关键的绝对差和模块应用差错复原机制,以对抗在工艺参数波动和/或工作电压超比例缩小(VOS)时可能产生的逻辑级时序错误.采用一个亚采样电路ISR-SSAD,将VOS技术和算法级容噪设计集成到绝对差和模块中,实现了差错检测和纠正,与原GEA结构相比,具有更低的功耗.计算结果表明,整个运动估计模块的功率节省可达16%.     

Modular VLSI architectures for computing the arithmetic Fouriertransform

Modular, area-efficient VLSI architectures for computing the arithmetic Fourier transform (AFT) are proposed. By suitable design of PEs and I/O sequencing, nonuniform data dependencies in the AFT computation which require nonequidistant inputs and assignment of Mobius function values are resolved. The proposed design employs 2N+1 PEs to compute 2N+1 Fourier coefficients. Each PE has an adder and a fixed amount of local storage, and one PE has a multiplier. I/O with the host is performed using a fixed number of channels. This results in simple PE organization, compared with those needed in known DFT/FFT architectures. The design achieves O(N) speedup. It uses significantly fewer PEs than designs in the literature and supports real-time applications by allowing continuous sequential input. It can be extended to achieve linear speedup in a fixed size array with 2p+1 PEs, 1⩽p⩽N     

Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations

Matching input/output (I/O) driver output resistance to transmission line impedance is critical for high-speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage, and temperature variations, that same calibration circuitry may perform improperly. This brief presents an I/O driver design that is less sensitive to process, voltage, and temperature variations. The proposed driver design provides a near linear or flat, output resistance response verses output voltage. Advantages of the proposed I/O driver architecture lie in applications where the output DC operating point may have a large variation, thus, reducing the error in matching output resistance.     

Conservative Approximation–Based Full‐Search Block Matching Algorithm Architecture for QCIF Digital Video Employing Systolic Array Architecture

This paper presents a power‐efficient hardware realization for a motion estimation technique that is based on the full‐search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register–based 2‐D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.     

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.