Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.     

低电压低功耗CMOS采样保持电路

设计了一个用于流水线型模数转换器的低压采样保持电路。为降低采保电路中运放的功耗,本文采用了增益补偿的采样保持电路结构,从而用简单的低增益运放达到高精度的效果。并从运放输出建立时间的角度对其输入电流进行优化。为了提高精度,降低采样开关的电阻并减小非线性误差,设计了信号相关自举电压控制的开关。仿真结果表明在1．8V的电源电压下,达到10bit的精度和50Mbit的采样率,整个采保电路的功耗仅为2．3mW。     

Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor

A compact, tunable CMOS transconductor is presented. The combined use of a Floating-Gate MOS (FGMOS) differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity. Measurement results for a prototype fabricated using a 0.8 m CMOS technology are provided, confirming on silicon the validity of the proposed approach.     

一种低压低功耗伪差分环形压控振荡器的设计

基于TSMC 28 nm CMOS工艺设计了一个伪差分结构的低压低功耗CMOS环形振荡器。电路包括偏置电路、环形振荡器和输出缓冲器。伪差分环形振荡器有五级延迟单元,延迟单元采用Maneatis对称负载。在Cadence Spectre上进行前仿真。结果表明,VCO工作在0.9 V电源电压下时,其频率调谐范围为0.65 GHz~4.12 GHz。在3.6 GHz以下频率范围内具有很好的调谐线性度。中心频率约为2.3 GHz时,其相位噪声为-79.06 dBc/Hz@1 MHz。输出缓冲电路能够实现轨对轨的输出摆幅,输出占空比可优化至50%。环形振荡器的功耗约为5.7 mW。     

Low-Voltage Analog Circuits Based on Wideband Capacitive Coupling

A technique for wideband low-voltage analog circuit operation based on capacitive signal coupling is discussed. Circuits based on this technique do not show the GB degradation of other low-voltage approaches based on floating-gate transistors. The technique is validated with simulations of a new CMOS mixer and experimental results of a test chip in a 0.5 m CMOS technology.     

A Low-Voltage Low-Power Rail-to-Rail Constant g m Transconductance Amplifier

In this paper, a low-voltage low-power rail-to-rail constant g _m transconductance amplifier (TA) is introduced. The supply voltages are set at (±1.5 V). The circuit depends on selecting the maximum transconductance (g _m ) to achieve an almost constant g _m over the entire common-mode (CM) range. The circuit is then used to realize a second-order 4 MHz lowpass filter consuming 530 W, and a fifth-order 450 kHz lowpass elliptic filter consuming 2.3 mW. Both filters can be integrated on silicon without any external connections.     

一种低压低功耗CMOS ULSI运算放大器单元

基于新型的折叠电流镜负载PMOS差分输入级拓扑、轨至轨(Rail-to-Rail)AB类低压CMOS推挽输出级模型、低压低功耗LV/LP技术和Cadence平台的实验设计与模拟仿真,采用2μmP阱硅栅CMOS标准工艺,得到了一种具有VT=±0.7V、电源电压1.1～1.5V、静态功耗典型值330μW、75dB开环增益和945kHz单位增益带宽的LV/LP运算放大器。该器件可应用于ULSI库单元及其相关技术领域,其实践有助于CMOS低压低功耗集成电路技术的进一步发展。     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

CMOS集成电路瞬态电流片外电流传感器电路

瞬态电流(IDDT)测试经常被看作是静态电流(IDDQ)测试的替代或补充,特别在深亚微米技术中,受到越来越多的关注。根据一种基于电荷的瞬态电流片外电流传感器电路,并在其基础上进行改进并对两阶多米诺加法器电路进行仿真实验,实验结果表明,改进后的电路能有效读取集成电路中的瞬态电流,从而实现瞬态电流的测试。     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.     

采用磁集成技术的低压大电流DC/DC变换器的仿真

运用回转器一电容模型可以很好的理解磁性器件，特别是复杂的集成磁件。文章运用磁导电容类比建模法建立了磁件的回转器一电容模型。在回转器一电容模型中，磁路由容性电路来模拟，绕组由双端口的回转器来代替。进行了采用磁集成技术的低压大电流DC／DC变换器的仿真。仿真电路拓扑是原边不对称半桥、副边倍流整流电路。磁集成变压器的结构是Wei Chen提出的原边绕于中柱的只在侧柱开气隙的倍流整流磁集成结构。建立了用SPICE语言描述的回转器仿真模型。仿真软件是MULTISIM2001。     

低功耗全集成微电子神经桥接电路的设计

神经传导束中断是脊髓损伤后功能障碍的主要原因。微电子神经桥是利用微电子芯片或模块旁路受损神经传导束,重建因神经通路中断而丧失的功能。设计了一种基于0.5μm CMOS工艺的低功耗、全集成微电子神经桥电路,版图面积为1.21 mm×1.18 mm。详细介绍了微电子神经桥核心单元电路低功耗两级运算放大器和输入/输出轨至轨运算放大器的设计。仿真结果表明,微电子神经桥接系统的通频带完全覆盖神经信号的频谱范围,增益可调至足够大,适用于神经信号探测和功能电激励。系统在±2.5 V供电情况下,功耗仅为3.4 mW,低功耗和系统全集成使得微电子神经桥向最终实现体内植入迈进了一步。     

A Low-Voltage Fully Differential MOSFET-C Bandpass-Based Voltage-Controlled Oscillator for Frequency Tuning

A low-voltage fully differential MOSEFT-C bandpass-based voltage-controlled oscillator for the purpose of frequency-tuning of filters is proposed. This oscillator is guaranteed to start oscillating and provide well-controlled amplitude. Experimental filters and the filter tuning circuit are designed to demonstrate its use. The performance of this circuit is shown by experimental results.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

MOSFET-Iike CNFET based logic gate library for low-power application： a comparative study

The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

CMOS Power-Efficient Buffers and Amplifiers

In this paper, some topologies of novel power-efficient single-ended and fully differential amplifiers and buffers are presented. The reduction of the power dissipation has been ensured through the application of an adaptive biasing architecture which gives a current dependent on the input differential voltage. This allows the minimization of the stand-by power consumption without affecting the transient characteristics. The proposed topology, implemented in a standard CMOS technology, has been applied in the design of input and output stages of low-power amplifiers and voltage buffers, considering them also in the fully differential version. Simulation and measurement results showing good general performance will be also presented.