Effect of interfacial oxide thickness on 1/f noise in polysilicon emitter BJTs

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.     

A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling

A new equivalent circuit method is proposed in this paper to de-embed the lossy substrate and lossy pads' parasitics from the measured RF noise of multifinger MOSFETs with aggressive gate length scaling down to 80 nm. A new RLC network model is subsequently developed to simulate the lossy substrate and lossy pad effect. Good agreement has been realized between the measurement and simulation in terms of S-parameters and four noise parameters, NF/sub min/ (minimum noise figure), R/sub n/ (noise resistance), Re(Y/sub sopt/), and Im(Y/sub sopt/) for the sub-100-nm RF nMOS devices. The intrinsic NF/sub min/ extracted by the new de-embedding method reveal that NF/sub min/ at 10 GHz can be suppressed to below 0.8 dB for the 80-nm nMOS attributed to the advancement of f/sub T/ to 100-GHz level and the effectively reduced gate resistance by multifinger structure.     

Characterization of GaAs FET's in Terms of Noise, Gain, and Scattering Parameters through a Noise Parameter Test Set

A method for the complete characterization of GaAs FET's in terms of noise parameters (F/sub o/,Gamma/sub on/, R/sub n/), gain parameters (G/sub ao/, Gamma /sub og/, R/sub g/), and of those scattering parameters ( S/sub11/, S/sub22/|,S/sub12/| S/sub21|, /spl angle/S/sub 12/S/sub 21/ ) that are needed for low-noise microwave amplifier design is presented. The instrumentation employed, i.e., a noise-figure measuring system equipped with a vectorial reflectometer, as well as the time consumption, are the same required for the determination of noise parameters only through conventional methods. The measuring setup and the experimental procedure are described in detail. Considerations about the computer-aided data processing technique are also provided. As an experimental result, the characterization of a sample device versus frequency (4-12 GHz) and drain current is reported. A comparison between the scattering parameters provided by the method and those measured by means of a network analyzer is also included.     

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

In this letter, we analyze the effects of temperature (from -50/spl deg/C to 200/spl deg/C) and substrate impedance on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF/sub min/) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum Q-factor (Q/sub max/), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency (f/sub SR/) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and Q-factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance (R/sub s/), the parallel substrate resistances (R/sub sub1/ and R/sub sub2/), and the resistance R/sub s1/ of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.     

Effects of spacer thickness on noise performance of bipolar transistors

The effects of spacer thickness on noise performance of a bipolar junction transistor with different emitter widths and operation frequencies are examined. The minimum noise figure (NF/sub min/) derived from the Y-parameters as well as the base (r/sub B/) and emitter resistance (r/sub E/) obtained from the device simulation is used as a measure of noise characteristics. Furthermore, the noise resistance (R/sub n/), optimum source admittance (Y/sub sop/), and the associated gain (G/sub A,assc/) are also given in this brief. To achieve the minimum value of NF/sub min/, the spacer thickness should be targeted to an optimal value, and its value is frequency and geometry dependent.     

An analysis of small-signal substrate resistance effect in deep-submicrometer RF MOSFETs

Two different explanations of the S/sub 22/ kink phenomenon in deep-submicrometer RF MOSFETs have been reported: Hjelmgren and Litwin (see IEEE Trans. Electron Devices, vol.48, no.2, p.397-399, 2001) attributed the phenomenon to the substrate resistance, while Lu et al. (see ibid., vol.49, no.2, p.333-340, 2001) concluded that it results from the transconductance, or simply speaking, the size of the transistor. In this paper, we extend the dual-feedback circuit methodology for the three-terminal FET model proposed by Lu et al. into a more general four-terminal model in order to account for the influence of the substrate resistance. Our results show that, for a given MOSFET, either substrate resistance or transconductance may cause a kink in S/sub 22/. In addition to the single kink, which results from the above two factors, the double kinks, which appear when the substrate resistance of a MOSFET is within a middle range (approximately 10/sup 2/ to 10/sup 4/ /spl Omega/), can also be accounted for by our extended model. Experimental data representative of 0.25 /spl mu/m gate MOSFETs are adopted to verify our theory. Excellent agreement between theoretical values and experimental data has been found, which indicates our theory can successfully explain the S/sub 22/ kink phenomenon in deep-submicrometer RF MOSFETs.     

Implementation of perfect-magnetic-coupling ultralow-loss transformer in RFCMOS technology

In this letter, we propose a single-turn multiple-layer interlaced stacked transformer structure with nearly perfect magnetic-coupling factor (k/sub IM//spl sim/1) using standard mixed-signal/RF CMOS (or BiCMOS) technology. A single-turn six-layer interlaced stacked transformer was implemented to demonstrate the proposed structure. Temperature dependence (from -25/spl deg/C to 175/spl deg/C) of the quality-factor (Q-factor), k/sub Im/, resistive-coupling factor (k/sub Re/), maximum available power gain (G/sub Amax/), and minimum noise figure (NF/sub min/) performances of the transformer are reported. State-of-the-art G/sub Amax/ of 0.762 and 0.904 (i.e., NF/sub min/ of 1.181 dB and 0.437 dB) have been achieved at 5.2 and 8 GHz, respectively, at room temperature, mainly due to the perfect magnetic-coupling factor and the high resistive-coupling factor. The present analysis is helpful for RF engineers to design ultralow-voltage high-performance transformer-feedback low-noise amplifiers and voltage-controlled oscillators, and other radio frequency integrated circuits which include transformers.     

Electrical-stress effects and device modeling of 0.18-/spl mu/m RF MOSFETs

In this paper, a novel microstrip-line layout is used to make accurate measurements of the minimum noise figure (NF/sub min/) of RF MOSFETs. A low NF/sub min/ of 1.05 dB at 10 GHz was directly measured for 16-finger 0.18-/spl mu/m MOSFETs, without de-embedding. Using an analytical expression for NF/sub min/, we have developed a self-consistent dc current-voltage, S-parameter, and NF/sub min/ model, where the simulated results match the measured device characteristics well, both before and after electrical stress.     

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.     

Compression mappings on primitive sequences over Z/(p/sup e/)

Let Z/(p/sup e/) be the integer residue ring with odd prime p/spl ges/5 and integer e/spl ges/2. For a sequence a_ over Z/(p/sup e/), there is a unique p-adic expansion a_=a_/sub 0/+a_/spl middot/p+...+a_/sub e-1//spl middot/p/sup e-1/, where each a_/sub i/ is a sequence over {0,1,...,p-1}, and can be regarded as a sequence over the finite field GF(p) naturally. Let f(x) be a primitive polynomial over Z/(p/sup e/), and G'(f(x),p/sup e/) the set of all primitive sequences generated by f(x) over Z/(p/sup e/). Set /spl phi//sub e-1/ (x/sub 0/,...,x/sub e-1/) = x/sub e-1//sup k/ + /spl eta//sub e-2,1/(x/sub 0/, x/sub 1/,...,x/sub e-2/) /spl psi//sub e-1/(x/sub 0/,...,x/sub e-1/) = x/sub e-1//sup k/ + /spl eta//sub e-2,2/(x/sub 0/,x/sub 1/,...,x/sub e-2/) where /spl eta//sub e-2,1/ and /spl eta//sub e-2,2/ are arbitrary functions of e-1 variables over GF(p) and 2/spl les/k/spl les/p-1. Then the compression mapping /spl phi//sub e-1/:{G'(f(x),p/sup e/) /spl rarr/ GF(p)/sup /spl infin// a_ /spl rarr/ /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) is injective, that is, a_ = b_ if and only if /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) = /spl phi//sub e-1/(b_/sub 0/,...,b_/sub e-1/) for a_,b_ /spl isin/ G'(f(x),p/sup e/). Furthermore, if f(x) is a strongly primitive polynomial over Z/(p/sup e/), then /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) = /spl psi//sub e-1/(b_/sub 0/,...,b_/sub e-1/) if and only if a_ = b_ and /spl phi//sub e-1/(x/sub 0/,...,x/sub e-1/) = /spl psi//sub e-1/(x/sub 0/,...,x/sub e-1/) for a_,b_ /spl isin/ G'(f(x),p/sup e/).     

Improved noise model for MESFETs and HEMTs in lower gigahertz frequency range

A noise model based on an equivalent circuit is applied to an HEMT. Besides the frequency dependence of the most important noise parameters (F/sub min/, R/sub opt/, X/sub opt/, R/sub N/) two apparent experimental facts are explained: the limited R/sub opt/, X/sub opt/ and the increase of R/sub N/ with decreasing frequency.<>     

Influences of sulfur passivation on temperature-dependent characteristics of an AlGaAs/InGaAs/GaAs PHEMT

The influences of (NH/sub 4/)/sub 2/S/sub x/ treatment on an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) are studied and demonstrated. Upon the sulfur passivation, the studied device exhibits better temperature-dependent dc and microwave characteristics. Experimentally, for a 1/spl times/100 /spl mu/m/sup 2/ gate/dimension PHEMT with sulfur passivation, the higher gate/drain breakdown voltage of 36.4 (21.5) V, higher turn-on voltage of 0.994 (0.69) V, lower gate leakage current of 0.6 (571) /spl mu/A/mm at V/sub GD/=-22 V, improved threshold voltage of -1.62 (-1.71) V, higher maximum transconductance of 240 (211) mS/mm with 348 (242) mA/mm broad operating regime (>0.9g/sub m,max/), and lower output conductance of 0.51 (0.53) mS/mm are obtained, respectively, at 300 (510) K. The corresponding unity current gain cutoff frequency f/sub T/ (maximum oscillation frequency f/sub max/) are 22.2 (87.9) and 19.5 (59.3) GHz at 250 and 400 K, respectively, with considerably broad operating regimes (>0.8f/sub T/,f/sub max/) larger than 455 mA/mm. Moreover, the relatively lower variations of device performances over wide temperature range (300/spl sim/510 K) are observed.     

SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in f/sub T/, f/sub max/, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

A novel frequency doubler using feedforward technique and defected ground structure

A novel design of frequency doubler using feedforward technique and defected ground structure (DGS) is proposed. The feedforward loop in the proposed frequency doubler suppresses the fundamental component (f/sub o/), and the DGS diminishes the higher order harmonics such as third, fourth, and so on. Due to the combination of feedforward structure and DGS, only the doubled frequency component (2f/sub o/) appears at the output port and the other unwanted components are suppressed excellently. A frequency doubler is designed at 1.85GHz of f/sub o/ by the proposed technique and measured. The measured output power of 2f/sub o/ is -3 dBm when the input power is 0 dBm. The obtained suppression of f/sub o/, 3f/sub o/, and 4f/sub o/ are 42.9, 19.2, and 29.7dB, respectively.     

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

The correlation between channel mobility gain (/spl Delta//spl mu/), linear drain-current gain (/spl Delta/I/sub dlin/), and saturation drain-current gain (/spl Delta/Idsat) of nanoscale strained CMOSFETs are reported. From the plots of /spl Delta/I/sub dlin/ versus /spl Delta/I/sub dsat/ and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R/sub SD,PSS/) to channel resistance (R/sub CH,PSS/) of strained CMOSFETs can be extracted. By plotting /spl Delta//spl mu/ versus /spl Delta/I/sub dlin/, the efficiency of /spl Delta//spl mu/ translated to /spl Delta/I/sub dlin/ is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the /spl Delta/I/sub dlin/-to-/spl Delta//spl mu/ sensitivity is maintained until R/sub SD,PSS/ becomes comparable to/or higher than R/sub CH,PSS/.     

Laterally scaled Si-Si/sub 0.7/Ge/sub 0.3/ n-MODFETs with f/sub max/>200 GHz and low operating bias

We report on the dc and RF characterization of laterally scaled, Si-SiGe n-MODFETs. Devices with gate length, L/sub g/, of 80 nm had f/sub T/=79 GHz and f/sub max/=212 GHz, while devices with L/sub g/=70 nm had f/sub T/ as high as 92 GHz. The MODFETs displayed enhanced f/sub T/ at reduced drain-to-source voltage, V/sub ds/, compared to Si MOSFETs with similar f/sub T/ at high V/sub ds/.     

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.