A CMOS Digitally Programmable Universal Current-Mode Filter

A new digitally programmable universal current-mode biquad filter is proposed. The filter is based on digitally controlled current followers (DCCFs). It utilizes gains of the DCCFs to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. All parameters of the proposed filter can be adjusted independently. Experimental results obtained from a 0.35-$mu$m standard CMOS chip are provided.      

Two digitally programmable gain amplifiers based on current conveyors

Two digitally programmable gain amplifiers based on current conveyors (CCIIs) are presented. The first digitally programmable gain amplifier consists of a CCII, an operational transconductance amplifier (OTA), and current mirrors. The second one is composed of current conveyor analogue switches (CCASs). Both proposed digitally programmable gain amplifiers do not need switches but they maintain the linear gain at any digital signal levels similar to the digitally programmable gain amplifier using switches; hence the proposed amplifiers are easier to realize, use narrower chip area, and consume lower power. The first proposed amplifier is verified by constructing the circuit using the CCII in an AD844 IC, the OTA in a CA3080 IC, and some bipolar current mirrors. The second proposed amplifier is verified by simulating the circuit using the parameters extracted from the layout (including parasitic capacitance) in the 0.25 μm MOS technology, the level 49 MOS model obtained through MOSIS is used. The results show that the operations of two proposed amplifiers are in accordance with the theories.     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

Digitally controlled CMOS current follower for low voltage lowpower applications

A novel digitally controlled CMOS current follower is proposed. The circuit is useful for low voltage low power high frequency applications. The DCCF operates from a 3 V supply in class AB mode and provides precise digitally programmable current gain without component spread. Experimental results from a 1.2 μm CMOS chip fabricated through MOSIS are provided     

CMOS digitally programmable filter for multi-standard wirelessreceivers

The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 μm chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards     

Digital frequency tuning technique based on current division for integrated active RC filters

A novel digital frequency tuning technique is presented for integrated active RC filters. Instead of varying the values of the capacitors or resistors as in traditional approaches, the proposed technique achieves frequency tuning by dividing the currents that flow from resistors to virtual grounds. Current division is performed through a digitally programmable current division network added at each virtual ground. The technique features compact size, wide tuning range and high linearity. Transistor level simulation results are presented to demonstrate the technique.     

基于现场可编程门阵列的数控延时器的设计

给出一种基于现场可编程门阵列(FPGA)的数控延时器的设计方法.首先详细介绍使用计数器的串联实现可控延时的方法,接着讨论不同延时范围下该数控延时器的改进方案,最后分析延时误差及延时精确度.延时器的外部接口仿照AD9501设计.     

Stable, digitally programmable active filters

The incorporation of digitally controlled gain linear amplifiers in the loops of a state variable active filter is shown to result in a filter digitally programmable in frequency and selectivity. The filter is shown to exhibit an order of magnitude higher temperature stability than programmable filters employing analog multipliers. Experimental results verifying the high temperature stability are presented for a filter programmable with 8 b over the frequency range 100 Hz to 25.5 kHz.     

Circuit implementation of a fully programmable and continuously slope tunable triangular/trapezoidal membership function generator

In this article, a fully programmable membership function generator (MFG) is proposed. This MFG is capable of generating triangular, trapezoidal as well as both S-shaped and Z-shaped membership functions simultaneously. Utilizing a differential pair as an analog switch leads to relax the design of fuzzy systems control part. This MFG has the ability of adapting itself with various fuzzy controllers which produce different control voltage ranges. Unlike the available reported literatures, this MFG uses a new analog programmable current mirror (APCM) instead of digitally programmable current mirrors to adjust the slopes of membership functions. Extensive time domain simulations have been carried out using Hspice by level 49 parameters (BSIM3v3) in standard CMOS technology to validate the effective performance of the proposed MFG.     

数字式可编程脉冲发生器

本文介绍了一种数字式可编程脉冲发生器。其电路简单,性能良好,可用来产生不同占空比的脉冲信号,并具有数字式可编程的功能。     

An automatic offset compensation scheme with ping-pong control forCMOS operational amplifiers

An automatic offset compensation scheme for CMOS operational amplifiers is presented. Offset is reduced by digitally adjusting the bias voltage of a programmable current mirror which is used as the load of the differential input stage. A 100% operating duty cycle is obtained by using a ping-pong structure. The offset compensation scheme is inherently time and temperature stable since the offset compensation is periodically performed with the ping-pong control. The proposed circuit has been fabricated using a 1.0 μm n-well CMOS process. The measured offset voltages of the test circuits are less than 400 μV in magnitude     

A fully programmable sampled-data analog CMOS filter with transfer-function coefficients determined by timing

A CMOS analog signal processor which is as programmable as a digital one is discussed. This processor does not use known switched-capacitor techniques, nor does it contain any selectable capacitor (or resistor) arrays. Instead, it operates on a pulsewidth control principle in which the value of each branch gain is determined by the duty cycle of a single digitally controlled analog transmission gate. A 4-/spl mu/m single-poly CMOS test IC containing all the critical analog functions was designed to demonstrate this principle at sampling frequencies up to 100 kHz. All of the processors described allow individual programming of each transfer function coefficient; one also features programmable topology, and another is capable of simultaneous multiple-signal multiple-transfer-function processing. A typical integrated fully programmable biquad shows 80-dB dynamic range.     

基于FPGA的可逆数制转码器设计

针对二一十进制（BCD）数据相互转换的FPGA实现目标,基于模块层次化的设计思想,提出了一种高效、易于重构的可逆转码器设计方案。并在FPGA（AlteraDE2）开发板上成功进行了12b可逆转码器的设计验证,实验结果表明该转码器通过端口参数配置就可以完全实现不同位数的二一十进制（BCD）数据间的相互转换。     

A real-time programmable switched-capacitor filter

Four independent real-time programmable switched-capacitor filters have been fabricated on a single NMOS chip. The filters are second-order sections with digitally programmable Q and center frequency. Either low-pass or bandpass functions are available by selecting the appropriate input. The device is microprocessor compatible and includes permanent programming capability as well as an on-chip oscillator. The circuit implementation, programming capability, and operation are described.     

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.     

Charge-domain FIR sampler with programmable filtering coefficients

A charge-domain sampling technique for realization of mixed-mode finite-impulse response (FIR) filters is presented. The method is based on weighting signal current samples integrated into a sampling capacitor with a set of parallel digitally controlled current-mode switches each carrying a unit current element. The fine achievable resolution and digital controllability of the filter tap coefficients allows realization of advanced programmable FIR filtering functions embedded into high-frequency signal sampling. Circuit-level simulation results of an example 50-MHz IF-sampler with a built-in 22-tap complex bandpass sinc/sup 3/ FIR function in 0.35-/spl mu/m CMOS are shown, demonstrating the feasibility of the presented method.     

Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories

This paper presents a word-line voltage generator for multilevel (ML) Flash memory programming. The required voltages are provided by a regulator supplied by an on-chip charge-pump voltage multiplier. A feedback loop including a digitally programmable resistive divider generates the staircase-shaped waveform needed for adequate ML programming accuracy as well as the read/verify voltage required for read and verify operations. A high-swing controlled-discharge circuit minimizes the settling time when switching from program to verify phases and vice versa. The same generator is used to provide the voltage required in read and in program mode, thus saving silicon area and minimizing current consumption. Experimental results of the proposed circuit integrated in a 4-level-cell 64-Mb NOR-type Flash memory are presented.     

A high-speed digitally programmable CCD transversal filter

A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible.     

一种数字可编程放大器的设计

文章介绍了一种高精度数字可编程放大器的设计原理，并给出了实验结果。该电路可广泛应用于数据采集系统、自适应伺服系统和量程自动转换的DVM等电子设备中。     

神经网络高精度权值的模拟电路实现

本文提出了一种电流模式4-bit可调权值模拟神经元电路,权值易存贮而且精度高。该电路可扩展为8-bit等多值分立权的神经元电路.文章扼要分析了神经元电路的工作原理,并用SPICE Ⅱ进行仿真,证明了这种电路的正确性。