Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate

A highly accurate closed-form approximation of frequency-dependent mutual impedance per unit length of a lossy silicon substrate coplanar-strip IC interconnects is developed. The derivation is based on a quasi-stationary full-wave analysis and Fourier integral transformation. The derivation shows the mathematical approximations which are needed in obtaining the desired expressions. As a result, for the first time, we present a new simple, yet surprisingly accurate closed-form expression which yield accurate estimates of frequency-dependent mutual resistance and inductance per unit length of coupled interconnects for a wide range of geometrical and technological parameters. The developed formulas describe the mutual line impedance behaviour over the whole frequency range ( i.e. also in the transition region between the skin effect, slow wave, and dielectric quasi-TEM modes). The results have been compared with the reported data obtained by the modified quasi-static spectral domain approach and new CAD-oriented equivalent-circuit model procedure.     

Miniaturized CBCPW bandpass filter basedon thin film polyimide on lossy silicon

This letter reports a miniaturized conductor-backed coplanar waveguide (CBCPW) bandpass filter (BPF) based on a thin film polyimide layer coated on a lossy silicon. With a 20-/spl mu/m-thick polyimide interface layer and back metallization, the interaction of electromagnetic fields with the lossy silicon substrate has been isolated, and as a result low-loss and low-dispersive CBCPW line has been obtained. The measured attenuation at 20GHz is below 1.2dB/cm, which is comparable with the CPW fabricated on GaAs. In addition, by using the proposed CBCPW geometry, a miniaturized Ku-band BPF was designed and its measured frequency response demonstrated excellent correlation with the predicted value which validated the performance of the proposed CBCPW geometry used for radio frequency integrated circuit interconnects and filter applications.     

芯片内互连线电阻和电感频变分布参数提取

本文使用导体截面矩量法提取芯片内互连线电阻和电感频变分布参数。根据芯片内多接地导体的情况重新推导了公式 ,实现了对算法的改进。研究了硅衬底导电率变化对金属绝缘半导体传输线的分布电阻和分布电感参数的影响。通过两个例子的计算 ,证明算法可应用于芯片内互连线参数提取。     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

A highly integrated millimeter-wave active antenna array using BCB and silicon substrate

A simple and inexpensive packaging scheme is implemented in the design of an active antenna array module. The package consists of etched wells in a silicon wafer in which the components of the module are placed. A benzocyclobutene (BCB) film covers the components and serves as a substrate for interconnections. Prefabricated metallic bumps on the components are used for connection through the BCB film, eliminating the need for wire bonds. Aluminum coating of the silicon wafer isolates the lossy substrate from the millimeter-wave circuitry. This packaging process is applied to form an array of four cavity-backed patch antennas and then integrate it with a down-converter. The resulting active antenna array down-converts a 39-GHz received signal. The only off-wafer interconnects are for the 16-GHz local-oscillator input and a 7-GHz IF output. The effect of the packaging on the down-converter is described and important design features are noted. A detailed loss analysis is conducted based on measurements of the array performance.     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

A W-Band Air-Cavity Filter Integrated on a Thin-Film Substrate

In this letter, a W-band air-cavity filter has been developed on a thin-film substrate using a lossy silicon substrate as a base plate, which is suitable for a mm-wave system-on-package. The lossy silicon suppresses a parasitic substrate mode excited in a thin-film substrate, while a coupling loss between a transmission line and a resonator is minimized by etching the backside of the lossy silicon substrate underneath the coupling area. In the backside etching process, 70 mum of silicon was left for mechanical support of the thin-film substrate. The resonator was fabricated using a low-cost silicon micromachining technique and was flip-chip integrated on a thin-film substrate. The fabricated air-cavity resonator showed an unloaded Q of 851 at a resonant frequency of 94.18 GHz. Improvement in the coupling loss by the backside etching process was verified with measurement results. The fabricated filter exhibited an insertion loss of 1.75 dB and a return loss better than 14.5 dB with a 1.3% 3 dB fractional bandwidth at a center frequency of 93.8 GHz.     

Thermal measurements of active semiconductor micro-structures acquired through the substrate using near IR thermoreflectance

Modern, high-density integrated circuits (IC) typically use a flip chip bonding technique to increase performance on a greater number of interconnects. In doing so, the active devices of the IC are hidden under the exposed substrate, which precludes the use of typical surface thermal characterization techniques. A near infrared thermoreflectance method is described such that the temperature of active semiconductor devices can be measured through the substrate. Experimental results were obtained through a 200 μm thick silicon substrate. Temperature resolution of 0.1 K and spatial resolution of 5 μm has been achieved. The Fabry-Perot effect, due to multiple reflections between the device and the back of the substrate, has been experimentally and theoretically analyzed. Techniques to enhance the spatial resolution will be discussed.     

Do chip size limits exist for DCA?

Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications     

Efficient computation of frequency-dependent parameters for on-chipinterconnects via two-dimensional FDTD and time signal predictiontechnique

An efficient two-dimensional finite difference time domain (2-D-FDTD) method combined with time signal prediction technique has been proposed for the frequency-dependent parameters computation of on-chip interconnects in high-speed integrated circuits (ICs). A graded mesh algorithm and lossy absorbing boundary condition are proposed and adopted in the 2-D FDTD analysis to reduce the number of spatial grid points in the simulation region. The introduction of time signal prediction technique to predict the future signal in the time domain or extract the parameters in the frequency domain of uniform transmission lines reduces the computation time drastically. With these, the substrate and conductor losses are both included in one analysis. This algorithm leads to a significant reduction in CPU time and storage requirements as compared with the conventional FDTD. The simulation results are in good agreement with the results obtained by other methods and measurements     

射频高损耗硅基双互连线建模

针对高损耗硅衬底,采用部分元等效电路法和准静磁积分公式,将衬底涡流等效为衬底镜像电流,建立射频硅基双互连线等效电路模型。该模型考虑了趋肤效应、邻近效应和衬底损耗对互连线串联电感Ls和串联电阻Rs频率特性的制约。通过与全波分析方法对比,验证了在20 GHz范围内由该模型导出的互连线等效电感L、等效电阻R误差均在8%以内。该模型可望应用于硅基射频集成电路设计。     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

A Millimeter-Wave System-on-Package Technology Using a Thin-Film Substrate With a Flip-Chip Interconnection

In this paper, a system-on-package (SOP) technology using a thin-film substrate with a flip-chip interconnection has been developed for compact and high-performance millimeter-wave (mm-wave) modules. The thin-film substrate consists of Si-bumps, ground-bumps, and multilayer benzocyclobutene (BCB) films on a lossy silicon substrate. The lossy silicon substrate is not only a base plate of the thin-film substrate, but also suppresses the parasitic substrate mode excited in the thin-film substrate. Suppression of the substrate mode was verified with measurement results. The multilayer BCB films and the ground-bumps provide the thin-film substrate with high-performance integrated passives for the SOP capability. A broadband port terminator and a V-band broad-side coupler based on thin-film microstrip (TFMS) circuits were fabricated and characterized as mm-wave integrated passives. The Si-bumps dissipate the heat generated during the operation of flipped chips as well as provide mechanical support. The power dissipation capability of the Si-bumps was confirmed with an analysis of DC-IV characteristics of GaAs pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency performances of a V-band power amplifier (PA). In addition, the flip-chip transition between a TFMS line on the thin-film substrate and a coplanar waveguide (CPW) line on a flipped chip was optimized with a compensation network, which consists of a high-impedance and low-impedance TFMS line and a removed ground technique. As an implementation example of the mm-wave SOP technology, a V-band power combining module (PCM) was developed on the thin-film substrate with the flip-chip interconnection. The V-band PCM incorporating two PAs with broadside couplers showed a combining efficiency higher than 78%.      

Si-YBaCuO intermixing and reactive patterning technique

A novel Si-YBaCuO intermixing technique has been developed for patterning YBaCuO superconducting thin films on both insulating oxide substrates (MgO) and semiconductor substrates (Si). The electrical, structural, and interfacial properties of the Si-YBaCuO intermixed system have been studied using resistivity, x-ray diffraction, scanning electron microscopy, x-ray photoelectron spectroscopy and Auger depth profiling measurements. The study showed that the reaction of Si with YBaCuO and formation of silicon oxides during a high temperature process destroyed superconductivity of the film and created an insulating film. On a MgO substrate, the patterning process was carried out by first patterning a silicon layer using photolithography or laser-direct-writing, followed by the deposition of YBaCuO film and annealing. For a silicon substrate, thin metal layers of Ag and Au were patterned as a buffer mask which defines the YBaCuO structures fabricated thereafter. Micron-sized (2-10 Μm) superconducting structures with zero resistance temperature above 77 K have been demonstrated. This technique has been used to fabricate current controlled HTS switches and interconnects.     

Highly Accurate Quasi-Static Modeling of Coupled Interconnects in CMOS Technology

A new analytic model is presented (the model is based on the induced current density distribution inside silicon substrate) to calculate frequency dependent mutual inductance and resistance per unit length of coupled on-chip interconnects in CMOS technology. The validity of the proposed model has been checked by a comparison with a quasi-TEM spectral domain numerical simulation and equivalent-circuit modeling procedure. It is found that the silicon semiconducting substrate skin effect must be considered for the accurate prediction of the high-frequency characteristics of VLSI interconnects.     

A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications     

FDTD法分析高速集成电路芯片内互连线

本文首次利用时域有限差分(FDTD)法分析了高速集成电路芯片内半导体基片上的有耗互连传输线的电特性.文中提出了有耗吸收边界条件,推导了不同媒质交界面上的边界条件通用格式.在FDTD分析的基础上,得到传输线各种参数的频变特性,为芯片内电路模拟提供了可靠的参数.     

A More Comprehensive Solution for Tri-Material Layers Subjected to Thermal Stress

Thermal stress due to mismatched coefficients of thermal expansion is a problem that has challenged the electronics packaging industry for decades. Analytical solutions are available in the literatures for a tri-material in which the sandwiched layer is a continuous layer. This author has earlier presented a solution for the sandwiched layer constituted of discrete interconnects; however, the solution ignores the shear deformation of the substrate layers. This paper removes the above assumptions and provides closed-form solutions for the shear, bending, and axial stresses in the sandwiched layer, as well as the in-plane stress in the substrate layers. The solutions are applicable to printed circuit board (PCB) assemblies constituting of an integrated circuit (IC) component, solder joints, and the PCB or to an IC component of tri-material layer structure. The solutions have been successfully validated with finite element analysis. Design analyses based on the analytical solutions have been performed for the shear and peeling stresses in the interconnects, the tensile fracture of IC chips due to in-plane stress, and the warpage of the IC component.     

A three-dimensional architecture for a parallel processingphotosensing array [silicon retina application]

A three-dimensional architecture for a photosensing array has been developed. This silicon based architecture consists of a 10 x 10 array of photosensors with 80 microns diameter, through chip interconnects to the back side of a 500 microns thick silicon wafer. Each photosensor consists of a 300 x 300 microns pn-junction photodiode. The following processes were used to create this photosensing architecture: 1) thermomigration of aluminum pads through an n-type silicon wafer; 2) creation of pn-junction photosensors on one side of the wafer; and 3) creation of aluminum pad ohmic contacts to the thermomigrated, through chip interconnects and the substrate on the back side of the wafer. The electrical and optical characteristics of the three-dimensional architecture indicates that it should be well suited as a photosensing framework around which a "silicon retina" could be built.