Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate

This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB//spl lambda//sub g/) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed.     

Experimental analysis of the effect of metal thickness on the quality factor in integrated spiral inductors for RF ICs

The effect of metal thickness on the quality (Q-) factor of the integrated spiral inductor is investigated in this paper. The inductors with metal thicknesses of 5/spl sim/22.5 /spl mu/m were fabricated on the standard silicon substrate of 1/spl sim/30 /spl Omega//spl middot/cm in resistivity by using thick-metal surface micromachining technology. The fabricated inductors were measured at GHz ranges to extract their major parameters (Q-factor, inductance, and resistance). From the experimental analysis assisted by FEM simulation, we first reported that the metal thickness' effect on the Q-factor strongly depends on the innermost turn diameter of the spiral inductor, so that it is possible to improve Q-factors further by increasing the metal thickness beyond 10 /spl mu/m.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Flip chip assembled MEMS inductors

High performance suspended MEMS inductors produced using a flip chip assembly approach are described. An inductor structure is fabricated on a carrier and then flip chip assembled onto a substrate to form a suspended inductor for RF-IC applications with significant improvement in Q-factor and frequency of operation over the conventional IC inductors. A spiral MEMS inductor has been successfully produced on a silicon substrate with an air gap of 26 /spl mu/m between the inductor structure and the substrate. The inductance of the device was measured to be /spl sim/2 nH and a maximum Q-factor of 19 at /spl sim/2.5 GHz was obtained after pad/connector de-embedding.     

Thermal effects in suspended RF spiral inductors

Self-heating effects on integrated suspended and bulk spiral inductors are explored. A dc current is fed through the inductors during measurement to emulate dc and radio frequency power loss on the inductor. A considerable drop in Q by /spl sim/18% at 36.5 mW is observed for suspended coils with 3-/spl mu/m aluminum metallization compared to reference inductors on bulk-Si. Simulations in Ansoft's ePhysics indicate that, due to the thermal isolation of the suspended coil, the power loss from resistive self-heating in the metal has to be transferred outwards through the metal turns. This also results in a thermal time constant. This time constant is measured to be /spl sim/10 ms, meaning that it can affect power circuits operating in pulsed mode.     

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

CMOS-compatible surface-micromachined suspended-spiral inductors for multi-GHz silicon RF ICs

Fully CMOS-compatible, highly suspended spiral inductors have been designed and fabricated on standard silicon substrates (1/spl sim/30 /spl Omega//spl middot/cm in resistivity) by surface micromachining technology (no substrate etch involved). The RF characteristics of the fabricated inductors have been measured and their equivalent circuit parameters have been extracted using a conventional lumped-element model. We have achieved a high peak Q-factor of 70 at 6 GHz with inductance of 1.38 nH (at 1 GHz) and a self-resonant frequency of over 20 GHz. To the best of our knowledge, this is the highest Q-factor ever reported on standard silicon substrates. This work has demonstrated that the proposed microelectromechanical systems (MEMS) inductors can be a viable technology option to meet the today's strong demands on high-Q on-chip inductors for multi-GHz silicon RF ICs.     

A high-Q quasi-planar filtering solution for 60-GHz applications

A low insertion loss 2.2% bandwidth two-pole cavity filter was fabricated at 60 GHz by bonding metallized lids on each side of a 250-/spl mu/m silicon substrate. The lids are made by dry etching of a 500-/spl mu/m silicon substrate. The same process is used to etch via holes on the intermediate substrate. The position of these via holes fixes the external coupling and the coupling between the resonators. The measured unloaded quality factor is lied on the height of the cavity (1.05 mm) and is around 1100.     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

Design and fabrication of zinc oxide thin-film ridge waveguides on silicon substrate with ultraviolet amplified spontaneous emission

Zinc oxide (ZnO) thin-film ridge waveguides have been designed and fabricated on n-type (100) silicon substrate. A filtered cathodic vacuum arc technique is used to deposit high-crystal-quality ZnO thin films on lattice-mismatched silicon substrates at 230/spl deg/C. A ridge waveguide of width /spl sim/2 /spl mu/m and height /spl sim/0.1 /spl mu/m is defined on the ZnO thin film by plasma etching. Room-temperature amplified spontaneous emission is observed with peak wavelength at /spl sim/385 nm under 355-nm optical excitation. It is found that the net optical gain of the ZnO thin-film ridge waveguides can be as large as 120 cm/sup -1/ at a pump intensity of /spl sim/1.9 MW/cm/sup 2/.     

Low-threshold lasing in novel microdisk geometries

We have fabricated arrays of semiconductor microdisks with diameters from 3.5-9 /spl mu/m using wet chemical etching in combination with epitaxial lift-off and metallic bonding techniques. The microdisks are supported on glass for higher optical confinement and to allow novel annular geometries. The optically pumped microdisks have high-Q (>2000) modes, low-pump thresholds (<20 /spl mu/W) and multimode lasing at liquid nitrogen temperatures. Successive modes are excited by temperature tuning the bandgap.     

A GSM LNA using mutual-coupled degeneration

This letter presents a low noise amplifier (LNA) input impedance matching technique using mutual coupled inductors. This scheme not only provides the required input impedance matching but also interstage impedance transformation for the cascoded transistor. The mutual coupled inductors also help to improve the circuit's reverse isolation. A 900-MHz global system for mobile communication LNA using this technique is designed and fabricated using 0.35-/spl mu/m standard complementary metal oxide semiconductor technology. It achieves a 17-dB gain, 3.4-dB noise figure, and -5.1-dBm IIP3. The LNA draws 5.6 mA from a single 2.3-V power supply.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

A miniaturized Wilkinson power divider with CMOS active inductors

A miniaturized Wilkinson power divider implemented in a standard 0.18-/spl mu/m CMOS process is presented in this letter. By using active inductors for the circuit implementation, a significant area reduction can be achieved due to the absence of distributed components and spiral inductors. The power divider is designed at a center frequency of 4.5GHz for equal power dividing with all ports matched to 50/spl Omega/. Drawing a dc current of 9.3mA from a 1.8-V supply voltage, the fabricated circuit exhibits an insertion loss less than 0.16dB and a return loss better than 30dB at the center frequency while maintaining good isolation between the output ports. The active area of the miniaturized Wilkinson power divider is 150/spl times/100/spl mu/m/sup 2/, which is suitable for system integration in monolithic microwave integrated circuit (MMIC) applications.     

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G/sub Amax/), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF/sub min/) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240/spl times/240 /spl mu/m/sup 2/ after the backside ICP etching. The values of G/sub Amax/ of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications.     

High-speed low-power silicon MESFET parallel multipliers

The design of fast low-power silicon LSI MESFET parallel multipliers is studied. The architecture of the multipliers and the designs of the functional blocks are discussed. The overall performance of the multipliers is estimated from the simulated performances of the functional blocks and from system simulations with a logic simulator. The actual performance of 8/spl times/8 and 10/spl times/10 bit TTL-compatible multipliers, fabricated with a 2.5 /spl mu/m silicon MESFET technology (1.5-2 /spl mu/m effective dimensions) is compared to the simulations.     

基于各向同性干法刻蚀的大面积悬空Al膜制备

热声传感器随着多孔硅的热致超声发射现象的发现越来越受到关注。热声传感器通过改变器件表面热量而在周围空气中产生交变压力,从而向外发出声波。热声传感器的关键器件是悬空金属薄膜。制备大面积悬空薄膜释放有一定的难度,需要考虑金属薄膜本身的应力与粘附效应。该文提出了两种基于各向同性干法刻蚀的制备金属薄膜的方法,利用XeF2/SF6制备悬空Al膜。由于XeF2与SF6气体刻蚀硅时对于Al有较高的选择比,XeF2对于硅是各向同性刻蚀且有很高的刻蚀速率,而通过设置感应耦合等离子体（ICP）刻蚀机的参数也可利用SF6达到各向同性刻蚀。基于上述特点制备了悬空Al膜,设计相应的制备流程,探索XeF2刻蚀机与ICP刻蚀机合适的刻蚀参数。所制备的悬空Al膜平整、无杂质,具有良好的形貌。     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A simple wide-band on-chip inductor model for silicon-based RF ICs

In this paper, we developed a simple wide-band inductor model that contains lateral substrate resistance and capacitance to model the decrease in the series resistance at high frequencies related to lateral coupling through the silicon substrate. The model accurately predicts the equivalent series resistance and inductance over a wide-frequency range. Since it has frequency-independent elements, the proposed model can be easily integrated in SPICE-compatible simulators. The proposed model has been verified with measured results of inductors fabricated in a 0.18-/spl mu/m six-metal CMOS process. We also demonstrate the validity of the proposed model for shielded inductors. The proposed model shows excellent agreement with measured data over the whole frequency range.     

Low-cost 1.55-/spl mu/m InGaAsP-InP spot size converted (SSC) laser with conventional active layers

We report the realization of a low cost 1.55-/spl mu/m spot size converted (SSC) laser using conventional SCH-MQW active layers. The laser consists of a rectangular gain section, a linear taper and a passive waveguide. The lateral taper and the passive waveguide are fabricated on the same lower SCH layer, using conventional photolithography and RIE (reactive ion etching). The device exhibits low beam divergence of 6.6/spl deg//spl times/10.9/spl deg/ and -2.2-dB coupling loss with a cleaved single-mode fiber. The 1-dB alignment tolerance is /spl plusmn/2.15 /spl mu/m in vertical direction and /spl plusmn/2.3 /spl mu/m in lateral direction, respectively.