Dynamical protection design with P-cycle parallel heuristic algorithm for optical networks

研究并总结了现有的各种自相似流量分析和预测的方法,同时采集局域网的动态流量数据,在此基础上生成自相似业务流.结合当今计算机界正在蓬勃发展中的并行计算,设计相关P圈配置并行算法,并将其应用到光网络的动态仿真中.     

Simulation of QRST integral maps with a membrane-based computer heart model employing parallel processing

The simulation of the propagation of electrical activity in a membrane-based realistic-geometry computer model of the ventricles of the human heart, using the governing monodomain reaction-diffusion equation, is described. Each model point is represented by the phase 1 Luo-Rudy membrane model, modified to represent human action potentials. A separate longer duration action potential was used for the M cells found in the ventricular midwall. Cardiac fiber rotation across the ventricular wall was implemented via an analytic equation, resulting in a spatially varying anisotropic conductivity tensor and, consequently, anisotropic propagation. Since the model comprises approximately 12.5 million points, parallel processing on a multiprocessor computer was used to cut down on simulation time. The simulation of normal activation as well as that of ectopic beats is described. The hypothesis that in situ electrotonic coupling in the myocardium can diminish the gradients of action-potential duration across the ventricular wall was also verified in the model simulations. Finally, the sensitivity of QRST integral maps to local alterations in action-potential duration was investigated.     

Modelling pipelines for embedded parallel processor system design

Four uses of order statistics for modelling parallel pipelines are proposed. The models are relevant to embedded applications using message-passing machines. A novel combination of queueing theory and order statistics, and a way of predicting degradation through any output-sequencing constraint are given. A simulation confirms the robustness of the analytic results     

A middleware service for employing and evaluating resource management algorithms in distributed networks

The first part of this paper introduces the design of a middleware‐based service which is valuable for distributed networks for mainly managing their resources. The second part evaluates the performance of a distributed intelligent network (D‐IN), which comprises the proposed service together with a resource management algorithm. We test the network's performance by building and emulating its basic functionality, based on distributed object technology (DOT), in a real environment. The resource management algorithm mainly aims at avoiding congestion and balancing load. Its implementation uses the ICALB algorithm (Comput. Commun. 2002; 25 (17):1548–1556) model. Its incorporation is succeeded through the use and implementation of the distributed middleware‐based service. It is a CORBA‐based service that is used for successfully managing resource management algorithms, such as ICALB, facilitate their operation, and solving classes of problems related to communications over the distributed network, sharing of resources spread over the network, scheduling, synchronization, and management of various tasks. By this means we argue that the method that we use can be employed for operating in various distributed networks. We also evaluate the network's performance by measuring various D‐IN node parameters with critical meaning and by showing the improvements that appeared to the D‐IN from the operation of both the ICALB algorithm and the proposed service. Copyright © 2005 John Wiley & Sons, Ltd.     

A batch‐type time‐true ATM‐network simulator—design for parallel processing

This paper presents a new type of network simulator for simulating the call‐level operations of telecom networks and especially ATM networks. The simulator is a pure time‐true type as opposed to a call‐by‐call type simulator. It is also characterized as a batch‐type simulator. The entire simulation duration is divided into short time intervals of equal duration, t. During t, a batch processing of call origination or termination events is executed and the time‐points of these events are sorted. The number of sorting executions is drastically reduced compared to a call‐by‐call simulator, resulting in considerable timesaving. The proposed data structures of the simulator can be implemented by a general‐purpose programming language and are well fitted to parallel processing techniques for implementation on parallel computers, for further savings of execution time. We have first implemented the simulator in a sequential computer and then we have applied parallelization techniques to achieve its implementation on a parallel computer. In order to simplify the parallelization procedure, we dissociate the core simulation from the built‐in call‐level functions (e.g. bandwidth control or dynamic routing) of the network. The key point for a parallel implementation is to organize data by virtual paths (VPs) and distribute them among processors, which all execute the same set of instructions on this data. The performance of the proposed batch‐type, time‐true, ATM‐network simulator is compared with that of a call‐by‐call simulator to reveal its superiority in terms of sequential execution time (when both simulators run on conventional computers). Finally, a measure of the accuracy of the simulation results is given. Copyright © 2002 John Wiley & Sons, Ltd.     

Parallel system design for time-delay neural networks

The authors develop a parallel structure for the time-delay neural network used in some speech recognition applications. The effectiveness of the design is illustrated by: (1) extracting a window computing model from the time-delay neural systems; (2) building its pipelined architecture with parallel or serial processing stages; and (3) applying this parallel window computing to some typical speech recognition systems. An analysis of the complexity of the proposed design shows a greatly reduced complexity while maintaining a high throughput rate     

An automated parallel simulation flow for cyber-physical system design

Parallel and distributed simulation (PDS) is often employed to tackle the computational intensity of system-level simulation of real-world complex embedded and cyber-physical systems (CPSs). However, CPS models comprise heterogeneous components with diverge semantics for which incompatible PDS approaches are developed. We propose an automated PDS flow based on a formal modeling framework—with necessary extensions—targeting heterogeneous embedded and CPS design. The proposed flow characterizes the sequential executable specification of a heterogeneous model and generates a PDS cluster. State-of-the-art graph partitioning methods are adopted and a new extensible constraint-base formulation of the model partitioning problem is developed. The applicability, effectiveness, and scalability of the proposed flow is demonstrated using case studies.     

用小型射频测试匣代替商用射频屏蔽室

明导国际公司（Mentor Graphics）针对PCB系统设计推出新型Expedition Enterprise流程工具，该工具有效解决了大型企业在进行复杂PCB设计时面临的并行设计、协同设计，以及系统集成等难题，还允许各公司将其设计数据与公司PLM系统、供应链以及制造系统实现集成，并与外包设计和制造建立沟通渠道。它使先进的PCB设计技术与数据库和设计数据管理以及统一约束编辑系统实现组合，能够有效缩短设计周期、降低设计成本。明导国际公司系统设计部业务发展总监David Wiens说：“Expedition Enterprise是面向当今最复杂PCB系统设计的技术领导者，它满足了客户进行大型PCB和系统设计的需要。”     

Optimum design of a banked memory with power management for wireless sensor networks

Wireless Networks - The ever-increasing complexity of applications covered by wireless sensor networks (WSNs) demands for increasing memory size, which in turn increases the power drain. It is well...     

以面向对象程序设计的教务管理系统的设计和实现

随着高校规模的不断扩大,以及高等教育制度改革的深化,实行学分制、本科导师制等给高等院校带来大量信息量的增加,这些都给教务系统的管理带来了巨大的挑战,因此,开发适应新形势下的教务管理系统成为当前教学改革的热点。本文结合当前高校教务管理的特点,利用面向对象技术,设计出教务管理系统,以此对当前的教务系统进行改进。     

Identity-based information security management system for personalcomputer networks

A network information security management system which authenticates and/or encrypts messages is proposed. Both authentication and key distribution are executed in a simple scheme. Once the system is set up, the transactions are done independently by the users involved, yet the amount of information that users must keep is small. The experimental implementation of the system on a personal computer network, using IC cards (smart cards) and digital signal processors, is described. The signal processors shorten calculation time and make the concept practical     

Integrated low-power communication system design for wireless sensor networks

Wireless sensor network systems are now being applied by an international community for critical applications in commerce, healthcare, and security. These systems have unique characteristics and face many implementation challenges. Among all, the requirement of long operating life for a wireless sensor node under limited energy supply imposes the most severe design constraints. This calls for innovative design methodologies to address this rigorous requirement. This article first provides an overview of wireless technologies for sensor networks. It then describes communication system, circuit design, and system packaging considerations. The selection of radio architectures and circuit techniques is discussed with an emphasis on the low-power implementation and operating characteristics that match requirements of sensor network application. Finally, the design, implementation, and performance of the most challenging component, a complete low-power CMOS receiver system, is presented to demonstrate these design principles.     

非线性系统神经网络L_2增益控制

针对很难求解HJ偏微分不等式解析解的问题,采取一种新的思想,给出了利用神经网络构造HJ不等式解的一种方法,并利用遗传算法进行神经网络权值的优化,使得Lyapunov函数满足HJ不等式,避免了求解HJ偏微分不等式.并在此基础上,给出基于HJ不等式的仿射非线性系统神经网络L2增益抗干扰控制器设计方法,以神经网络的形式给出L2增益控制器的一般结构.仿真结果表明,提出的控制器设计方法是可行的,实现了闭环系统为从外界干扰到系统输出是有限增益L2稳定的.     

非线性系统神经网络L2增益控制

针对很难求解Ⅲ偏微分不等式解析解的问题,采取一种新的思想,给出了利用神经网络构造HJ不等式解的一种方法,并利用遗传算法进行神经网络权值的优化,使得Lyapunov函数满足HJ不等式,避免了求解HJ偏微分不等式。并在此基础上,给出基于HJ不等式的仿射非线性系统神经网络L2增益抗干扰控制器设计方法,以神经网络的形式给出厶增益控制器的一般结构。仿真结果表明,提出的控制器设计方法是可行的,实现了闭环系统为从外界干扰到系统输出是有限增益L2稳定的。     

一种基于RFID的涉密载体管理系统设计

为加强涉密载体的有效管控,解决涉密栽体管理时间和空间上存在盲区、遗失后发现不及时、查找困难等问题,提出了一种基于RFID技术的涉密栽体管理系统实现方案.对该系统的构成和实现功能、硬件系统组成及设备选择、软件系统组成及涉密栽体实时区域定位等问题进行了分析.实验测试表明,该系统已部分实现了设计的功能,可提高涉密栽体的技术管控手段和效率.     

Low power & mobile hardware accelerators for deep convolutional neural networks

This article provides a comprehensive review of recent developments in the field of computational hardware for mobile low power machine learning hardware accelerators. The article provides an introduction to neural networks, convolutional neural networks and details recent developments in state of the art deep convolutional neural networks. The key considerations in the design of low power hardware accelerators are discussed with reference to a conceptual system. Strategies for reducing the energy cost of memory access and computation in state of the art hardware accelerators are detailed. This includes techniques such as dataflow, reduced precision, model compression and sparsity. Recent reported digital mobile accelerators for deep convolutional neural networks with power consumptions of less than 3.3 W are observed to have 4x-20x better efficiency than the reference GPU accelerator at 16-bit precision, and can achieve 20x-1171x better efficiency at less than 4-bit precision. Efficiency improvements of 20x-1171x over a GPU is observed for reported mobile accelerators with reduced precision.     

A new handoff management system for heterogeneous wireless access networks

In heterogeneous wireless access networks, each mobile terminal may frequently need to change its base station (BS); this change is called a ‘handoff’. BSs have static parameters, which are related to their radio access technologies (RATs); however, they also contain dynamic parameters such as load and signal quality. Therefore, the problem of handoff decision includes two subproblems of RAT selection and BS selection. In this paper, first a ‘heterogeneous handoff management system’ for gathering all different required parameters is proposed. Second, a RAT Selection algorithm based on analytic hierarchy process and a BS Selection algorithm based on data envelopment analysis are designed. Finally, by means of ‘weight restriction’ technique, we develop a method for studying the impact of RAT Selection parameters on the performance of the network. Simulation results indicate that RAT Selection parameters have significant impact on the bandwidth utilization, energy consumption and the whole satisfaction of the users in heterogeneous wireless access networks.Copyright © 2012 John Wiley & Sons, Ltd.     

'Synchronous' CDMA demonstration for fibre-optic networks with optical processing

'Synchronous' code-division multiple-access (S/CDMA) for fibre-optic networks with optical processing is investigated. A two-user experiment demonstrating the feasibility of such a network is performed at 10 Mbit/s (500 Mchip/s) using modified prime sequence codes and optical processing. Fibre-optic delay-lines are used for code sequence generation and correlation without using fast electronic components. An environment in which S/CDMA would be particularly suitable is discussed.<>     

Rate management in multiuser detection based MAC design for ad hoc networks

We propose a framework that produces synergy between Medium Access Control (MAC) and physical layers in order to increase the users’ individual throughput in a high-capacity CDMA ad hoc network. The MAC layer supports a multiuser detection based access protocol. Users send data packets at different rates, depending on the fading channel state. The framework is based on an LMS (Least Mean Square) prediction algorithm that estimates channel gain at the physical layer. The performance of the scheme is evaluated by simulations. Multiuser detection typically triples the throughput of ad hoc networks but our prediction-based scheme further doubles this metric. The main advantage of the proposed scheme is its flexibility and efficiency in a wide range of data rates and target bit error rates. It is also well fitted to support high-quality multi-media transmissions, and to improve the performance of applications that require high quality of service (QoS).