Fabrication of 0.5-μm structures by dry electron lithography and anisotropic plasma etching

A method for the fabrication of submicron (~0.5 μm) structures is presented. It includes the plasma formation of a three-layer mask, electron-beam exposure, plasma development, and anisotropic plasma etching of a resist and silicon oxide. The development in a fluorine-containing plasma forms the negative image of the exposed pattern (a set of parallel strips). The minimum resolution was 0.5 μm at the exposure dose 8 x l0^-4C/cm². The minimum exposure dose at which separate lines are developed was equal to 1 x 10^-4 C/cm²     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

A novel memory cell for multiport RAM on 0.5 μm CMOSSea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V     

Multipass diode-pumped Nd:YAG optical amplifiers at 1.06 μm and1.32 μm

We have built two versions of a diode-pumped Nd:YAG amplifier using a compact multipass confocal geometry with a fiber-coupled input. This confocal geometry provided efficient power and high gain in a volume of approximately 100 cm³. When pumped with a commercially mature 2 W 809 nm laser diode, the 1.06 μm version produced 460 mW and a small signal gain of 51 dB. The 1.32 μm version produced 170 mW and a small signal gain of 29 dB. Such an efficient amplifier, especially at 1.32 μm would be useful as a power booster in fiber optic telecommunications     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors     

Techniques for reducing the reverse short channel effect in sub-0.5μm CMOS

Experimental evidence is presented demonstrating that the reverse short channel effect (RSCE) is initiated by damage from the source-drain implants which, in turn, causes defect-enhanced diffusion of the channel dopants toward the gate oxide interface. Several process options that attempt to modify the diffusion of the channel implants, such as channel doping profile engineering, vacancy injection into the silicon substrate through sputter-etch damage, and TEOS depositions on silicon followed by rapid thermal annealing, are described which reduce the magnitude of the reverse short channel effect. This often results in an increase in device short channel margin of as much as 50 nm and a concomitant increase in the n-channel drive current of as much as 10%     

High-speed performance of OMCVD grown InAlAs/InGaAs MSMphotodetectors at 1.5 μm and 1.3 μm wavelengths

A report is presented on the fabrication of high-speed In_0.53 Ga_0.47As metal-semiconductor-metal (MSM) photodetectors incorporating a high-quality lattice-matched InAlAs barrier enhancement layer, grown by organometallic chemical vapor deposition (OMCVD). Fast responses of ~55 ps full-width half-maximum at 1.5 μm and ~48 ps at 1.3 μm wavelengths are observed, corresponding to intrinsic device bandwidths of ~8 GHz and ~11 GHz, respectively. The absence of any tail to the pulse response, and of any low-bias DC gain, indicates a low-trap density at the InAlAs/InGaAs heterointerface. Bias independent dark currents of 10-20 μA are observed below breakdown, which occurred at >30 V in devices with a 500-A-thick InAlAs layer     

碲镉汞p型接触孔低损伤干法刻蚀技术研究

对碲镉汞材料干法刻蚀损伤进行研究,采用感应耦合等离子体干法刻蚀技术、湿法腐蚀方法完成碲镉汞接触孔刻蚀,通过扫描电子显微镜和激光扫描显微镜分析刻蚀后样品的表面形貌,利用伏安特性曲线分析刻蚀样品的表面损伤。实验结果表明,干法刻蚀工艺极易造成碲镉汞p型接触孔表面反型,提出了一种新型的干法混合刻蚀技术,该技术通过两步干法刻蚀工艺实现,有效地降低了刻蚀引入的表面损伤。     

Effects of plasma etching chemistry and post-processing on themechanical adhesion and electrical contact of double polysilicon layerstructures

Double polysilicon layer structures separated by a silicon nitride layer are frequently used as structural multilayers in surface micromachining. In this paper the effect of three types of plasma etching chemistries for nitride patterning and post-processing on the characteristics of both mechanical adhesion and electrical contact resistance between the two polysilicon layers is investigated. It was found that all three chemistries yielded good mechanical adhesion between the two polysilicon layers. Both the chemistry based on CF₄ /SF₆, with a poor selectivity (0.7) of etching nitride over the underlying polysilicon layer, and the chemistry based on CHF ₃/CF₄, with a selectivity of 3, provided good electrical contact. The chemistry based on CHF₃/N₂, which yielded a selectivity of 15, on the other hand, resulted in a polymer film between the two polysilicon layers, resulting in electrical insulation. This polymer film can be effectively removed by using post-processing, which involves in-situ oxygen plasma treatment. Therefore, a chemistry such as that based on CHF₃/CF₄ can be applied when the lower polysilicon thickness allows a moderate selectivity, whereas the CHF₃/N ₂ chemistry is favored when high-selectivity is required. The latter, however, requires in-situ post-processing     

Impact of pad and gate parasitics on small-signal and noisemodeling of 0.35 μm gate length MOS transistors

Microwave noise performance of p and n-type MOSFETs fabricated on the. same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. At low drain currents, the gate parasitic circuit was involved in the modeling to explain the observed kinks and loops in the s-parameters. Simulation of the noise parameters for p and n-type devices, measured in the 2-26 GHz frequency range, was performed by using extracted small-signal models of the transistor in connection with parasitic pad and gate circuits. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters     

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.     

Fabrication of 1.55 μm VCSELs on Si using metallic bonding

Using AuGeNiCr multilayered metals as the wafer bonding medium, long-wavelength GaInAsP/InP vertical cavity surface emitting lasers employing Al-oxide/Si as the upper and lower distributed Bragg reflectors were fabricated on Si substrate with the bonding interface formed outside the vertical cavity surface emitting laser cavity. Laser emission at 1.545 μm was measured under pulsed operations near room temperature. The low-temperature metallic bonding process demonstrates a great potential in device fabrication     

The effect of remote plasma nitridation on the integrity of theultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 Å~22 Å. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 Å     

InP microdisk lasers on silicon wafer: CW room temperatureoperation at 1.6 μm

Microdisk lasers are fabricated in an InP:InGaAs MQW heterostructure transferred onto silicon. The CW room temperature laser operation of such devices at 1.6 μm is reported     

Generation of micro- and THz-waves at 1.5 μm by dual-frequencyEr:Yb laser

A promising technique for generating discrete-tunable beat-note signals is presented and investigated. Two tunable fibre gratings provide external feedback to an Er:Yb laser. Beat-notes from 60 GHz up to ~2 THz are achieved. Power equalisation is discussed and the partition noise is measured     

Optimization of ohmic contact and adhesion on polysilicon in MEMS-NEMS wet etching process

This paper presents the optimization of polysilicon doping and metallization to form ohmic contact with etching resistance. Indeed, polysilicon doped by ion implantation and ohmic contacts are an important and interesting part of integrated circuit technology or MEMS and NEMS. LPCVD-polysilicon doping parameters, such as ion energy, dose, and annealing were investigated. In particular a superficial implantation realized after a deep implantation enables one to slightly decrease the polysilicon resistivity while the contact resistance is reduced. And ohmic contacts with wet etching resistance were realized by depositing the different metallization stacks. We demonstrate that ohmic contact pad Cr/Pt/Au has provided a good adhesion on LPCVD-polysilicon after wet etching.     

Improving the RF performance of 0.18 μm CMOS with deep n-wellimplantation

The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F _t) and maximum oscillation frequency (F_max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F_t and 25% increase in F_max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications     

CMOS 2.4 μm chaotic oscillator: experimental verification ofchaotic encryption of audio

The authors report the first experimental verification of chaotic encryption of audio using custom monolithic chaotic oscillators. We use G_m-C techniques to realise a chaotic modulator/demodulator IC that implements a 3rd-order nonlinear differential equation. This has been fabricated in 2.4 μm double-poly technology and includes on-chip tuning circuitry based on amplitude detection. Measurements demonstrate how to exploit the synchronisation between two of these ICs for encrypted transmission     

Short-channel-effect free 0.18 μm MOSFET bytemperature-dimension combination scaling theory: design and experiment

We have fabricated 77 K deep-submicron MOSFETs on the basis of the temperature-dimension combination scaling theory (CST). The 77 K MOSFETs with 1-V supply voltage are designed from a 300 K MOSFET with 4-V supply voltage. The fabricated 77 K 0.18 μm device has exhibited fully scaled characteristics. The subthreshold swing (S) and the threshold voltage (V_th) of the 77 K device are found to be 1/4≈77 K/300 K of those of the 300 K device. Furthermore, S and V_th are achieved to be 27 mV/dec and 0.21 V without short-channel effect degradation     

Structural and electrooptical characteristics of quantum dotsemitting at 1.3 μm on gallium arsenide

We present a comprehensive study of the structural and emission properties of self-assembled InAs quantum dots emitting at 1.3 μm. The dots are grown by molecular beam epitaxy on gallium arsenide substrates. Room-temperature emission at 1.3 μm is obtained by embedding the dots in an InGaAs layer. Depending on the growth structure, dot densities of 1-6×10¹⁰ cm^-2 are obtained. High dot densities are associated with large inhomogeneous broadenings, while narrow photoluminescence (PL) linewidths are obtained in low-density samples. From time-resolved PL experiments, a long carrier lifetime of ≈1.8 ns is measured at room temperature, which confirms the excellent structural quality. A fast PL rise (τ_rise=10±2 ps) is observed at all temperatures, indicating the potential for high-speed modulation. High-efficiency light-emitting diodes (LEDs) based on these dots are demonstrated, with external quantum efficiency of 1% at room temperature. This corresponds to an estimated 13% radiative efficiency. Electroluminescence spectra under high injection allow us to determine the transition energies of excited states in the dots and bidimensional states in the adjacent InGaAs quantum well