Variation of lateral doping as a field terminator for high-voltage power devices

In this brief a new concept for high-voltage planar junctions is presented. The necessary widening of the space-charge region at the junction surface is obtained by implantation through small openings in the oxide mask and subsequent drive-in, leading to a controlled smeared-out dopant distribution. Compared to other planar junctions, this concept also yields a gain in active chip area. Experimental results show the validity of the concept.     

A new complementary dielectric isolation process for high-voltage devices

A new complementary dielectric isolation process for high-voltage devices has been developed. Both p-type and n-type islands are formed on one chip with a combination of epitaxial growth, anisotropic etching, and some self-alignment techniques. In this technique, the shape, depth, and impurity profile of the islands are precisely controlled, so that the breakdown voltage of more than several hundred volts is easily obtained for the devices formed in the islands.     

Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process

A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC(digital-to-analog converter).With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS(N-type lightly-dosed-drain in MOS) with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the conver...     

高压BiCMOS工艺中耗尽型NJFET的设计与应用

摘 要：本文提出了一种新型的兼容高压BiCMOS工艺的耗尽型NJFET,并实际研制了一种四路12位数模转换器。研制的NJFET夹断电压-1.5V,击穿电压17V;带轻掺杂漏区的高压NMOS管开启电压1.0V,击穿电压35V;齐纳二极管的正向电压5.5V。使用该耗尽型NJFET及其兼容工艺研制的四路12位数模转换器的基准温度系数为±25ppm/℃,微分误差小于±0.3LSB,线性误差小于±0.5LSB,还可以广泛应用于其他高压数模/模数转换器的研制。     

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the device's critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.     

用于横向RESURF器件击穿电压优化的电荷分配模型

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF （reduced surface field） structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration （per unit area） of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.     

A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.     

Bias temperature reliability of p-channel high-voltage devices

Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions.An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device.The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.     

Evaluation of high-voltage 4H-SiC switching devices

In this paper, the on-state and switching performance of 4H-SiC UMOSFETs, TIGBTs, BJTs, SIThs, and GTOs with voltage ratings from 1 to 10 kV are simulated at different temperatures. Comparison with silicon devices highlights the advantages of SiC technology. SiC BJTs suffer the same problem as Si BJTs, namely the degradation of current gain with increased voltage rating which makes them unsuitable for applications above 4 kV. SiC MOSFETs dominate applications below 4 kV for their attractive conduction performance and advantages such as ease of use. Above 3 kV, SiC MOSFETs are not as attractive as SiC bipolar devices because of their high on-state voltages. In the voltage range simulated, SiC IGBTs, SIThs, and GTOs have comparable current handling ability. Considering the GTOs slow switching speed and drive complexities, IGBTs and SIThs are a better choice in the voltage range 4-10 kV. Calculations based on conduction loss and switching loss indicate that SiC SIThs are superior to IGBTs except in high-temperature and high-frequency applications where IGBTs are better. The need to provide a large gate current during turnoff and turn-off failure caused by gate debiasing, decreases the attractiveness of the SITh     

Design of a high-voltage GTO chopper for traction drive

A chopper operating at 4000 V and 800 A RMS using two large series-connected GTOs (4500 V, 2500 A) is designed. The series connection of GTOs is considered, including criteria for the selection of GTOs, design of snubbers, and adaption of GTO controls. The advantages and drawbacks of the strategies used are discussed. Detailed experimental results concerning the GTOs' commutations and the snubber circuits are presented. The influence of important parameters, such as the load current on the transient voltage distribution on the GTOs is discussed. Because series connection of GTOs is liable to be used in the high-voltage converters of rail traction systems, two industrial realizations are proposed     

Monolithic integration of 5 V CMOS and high-voltage devices

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are available in this technology, including bipolar transistors, lateral MOS gate power devices, and high-voltage p-channel power devices     

Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

The optimizations to metal gate structure and film process were extensively investigated for great metalgate stress(MGS) in 20 nm high-k/metal-gate-last(HKVMG-last) nMOS devices.The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values(0 to—6 GPa) was implemented in the device simulation along with other traditional process-induced-strain(PIS) technologies like e-SiC and nitride capping layer.The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down.In addition,the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated.Also with a new method of fully stressed replacement metal gate(FSRMG) and using plane-shape-HfO to substitute U-shape-HfO,the effect of MGS was improved.For greater film stress in the metal gate,the process conditions for physical vapor deposition(PVD) TiN-x- were optimized.The maximum compressive stress of—6.5 GPa TiN_x was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.     

20纳米nMOS器件中应力金属栅结构设计与薄膜工艺优化

对于如今的CMOS集成工艺,应变金属栅是关键的工艺引入应变技术（PIS,process-induced-strain）之一。在本文中,为了在20nm高K金属栅后栅工艺的nMOS器件中得到较高栅应力,我们对金属栅结构和薄膜工艺的优化进行了大量的研究。通过TCAD工具对工艺和器件的仿真,我们研究了先进应变金属栅技术对器件性能的影响。带有不同栅应力（0GPa~-6GPa）的金属栅电极被应用在器件的仿真中,与此同时,其他PIS技术,如e-SiC 和氮化物应力层也被应用于器件中。随着器件尺寸的减小,应变金属栅对器件中沟道载流子输运有巨大的提高作用。此外,一种新型的角栅电极结构被提出,角度与沟道应力的关系被研究。同时,一种新的全应变金属填充栅以及用平板型氧化铪层代替U型氧化铪层,都能够提高应变金属栅的效果。为了在金属栅中得到更大应力的薄膜,我们优化了物理汽相淀积氮化钛的工艺条件。在氮气流量大约6sccm,较高溅射功率和较薄膜厚的情况下我们得到了最大的压应力-6.5GPa。     

2 m级望远镜主动调节侧向支撑机构设计与优化

基于某2 m轻量化SiC主镜,设计了一种新型主动调节侧支撑机构。先分析常用的侧向支撑机构的结构形式和特点;再设计由位移促动器、柔性铰链结构和嵌入杠杆系统等部件组成的主动调节支撑机构;最后,对机构的支撑力和移动量进行有限元分析,并且搭建实验平台,对其进行刚度和调节能力测试。试验结果表明:当支撑力为562.55 N时,杠杆结构中位移促动器承受的力为97.57 N,大大降低了位移促动器的刚度、强度要求;位移促动器行程为0.065 mm,是支撑杆中的22倍,大大降低了位移促动器分辨率要求;试验测得刚度为1 225 N/mm,达到了设计要求,表明这种柔性杠杆支撑系统具有很好的工程应用能力。     

Design of optical circuit devices based on topology optimization

We apply a design method based on topology optimization technique to optical waveguide devices. In our approach, after a refractive index profile in a design region is automatically generated using a topology optimization method, the obtained structure is redefined using primitive geometries with some design parameters and those parameters are optimized by a sequential linear programming. As numerical examples, we demonstrate how the method can be used for 90/spl deg/ bends and T-branching waveguides with arbitrary splitting ratio.     

Micromachining technology for lateral field emission devices

We demonstrate a range of novel applications of micromachining and microelectromechanical systems (MEMS) for achieving efficient and tunable field emission devices (FEDs). Arrays of lateral field emission tips are fabricated with submicron spacing utilizing deep reactive ion etch (DRIE). Current densities above 150 A/cm² are achieved with over 150·10⁶ tips/cm². With sacrificial sidewall spacing, electrodes can be placed at arbitrarily close distances to reduce turn-on voltages. We further utilize MEMS actuators to laterally adjust electrode distances. To improve the integration capability of FEDs, we demonstrate batch bump-transfer of working lateral FEDs onto a quartz target substrate     

一种采用单信号控制的新型高压高低侧功率器件

Novel high-voltage, high-side and low-side power devices, whose control circuits are referred to as the tub, are proposed and investigated to reduce chip area and improve the reliability of high-voltage integrated circuits. By using the tub circuit to control a branch circuit consisting of a PMOS and a resistor, a pulse signal is generated to control the low-side n-LDMOS after being processed by a low-voltage circuit. Thus, the high-voltage level-shifting circuit is not needed any more, and the parasitic effect of the conventional level-shifting circuit is eliminated. Moreover, the specific on-resistance of the proposed low-side device is reduced by more than 14.3% compared with the conventional one. In the meantime, integrated low-voltage power supplies for the low-voltage circuit and the tub circuit are also proposed. Simulations are performed with MEDICI and SPICE, and the results show that the expectant functions are achieved well.     

Double positive beveling: A better edge contour for high-voltage devices

A theoretical analysis is made of the field distribution near the surface of p-n-p structures with double positive edge geometry. This geometry offers in principle the possibility of avoiding the limitations and disadvantages inherent in the use of negative bevel angles. The results show that the reduction of the maximum field at the surface is not as easy as for the case of a simple positive bevel angle and that consequently the passivation of the surface may present more problems. Nevertheless, it is demonstrated that this geometry offers a number of great advantages and presents a real alternative for use in future high-voltage devices. A number of devices, dimensioned for a breakdown voltage of 6 kV, were made with this edge geometry. The measurements show that the reverse current corresponds to the thermally generated current in the space-charge layer and that no significant current flows at the surface. The breakdown voltage corresponds to the theoretical breakdown voltage in the bulk, unlike in the case of double negative beveling. The advantages of this geometry with respect to the conventional negative bevel angle are no significant reduction of active area, no dependence on the doping profile, and no limitation in voltage. A disadvantage, however, is the presence of higher fields at the surface.     

Design and optimization of LDMOS-SCR devices with improved ESD protection performance

The lateral diffusion metal-oxide semiconductor embedded silicon controlled rectifier (LDMOS-SCR) devices with optimized structures and layouts for improving the electrostatic discharge (ESD) protection ability have been proposed. The devices are designed and fabricated in 0.25-μm, 0.35-μm and 0.5-μm Bipolar-CMOS-DMOS processes. Firstly, by designing an appropriate stripe resistance in series with the source of the LDMOS-SCR, the holding voltage of the proposed high resistance LDMOS-SCR (HRLDMOS-SCR) increases. Secondly, by inserting a floating Zener-diode into the LDMOS-SCR, the trigger voltage of the modified Zener-diode triggered LDMOS-SCR (ZTLDMOS-SCR) decreases. Finally, the ZTLDMOS-SCR is further optimized by using a ring layout and incorporating a square source resistance, resulting in a significantly improved figure of merit in comparison to traditional LDMOS-SCR devices. The optimized ZTLDMOS-SCR devices are very attractive for constructing effective and latch-up immune high voltage ESD protection solutions in power integrated circuits.     

一种高压大电流PIN管开关驱动器的设计

介绍了一种PIN管开关驱动电路.该电路采用了控制信号与高压源相隔离的方法,可支持300 V以内的高压,并具有800 mA的电流驱动能力,驱动电路的开关切换时间小于2.6 μs.通过对高压器件的防击穿保护,并增加适当的延时电路,大幅度提高了驱动电路的工作稳定性.该电路可应用到高电压、大电流、高功率容量、高速切换的PIN管...