Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power SVg,eqfor n-channel MOSFET's has a 1/fα spectrum (0.8 < α < 0.95) above 10 µA, even for sealed-down devices with channel lengths LGof 2 µm. The SVg,eqis clearly proportional to 1/Leffdown to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 10¹²cm^-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.     

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n⁺poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm²/V.s. The drain-to-source breakdown voltage exceeds -20 V.     

A compatible NMOS, CMOS metal gate process

An MOS LSI technology is presented, which allows the efficient fabrication of n-MOS and CMOS circuits on the same chip, a capability, which has become highly desirable in view of recent advances in circuit design, particularly analog-digital interfaces. The process starts from a p-type substrate. An n-well is formed by ion implantation. An additional implantation simultaneously sets the p-channel and n-channel threshold voltages as well as the field threshold above the substrate. The implanted field provides high density and simple processing. A third implantation step adjusts the threshold voltage of the n-channel depletion load transistor. Supply voltages up to 20 V are possible. Process modeling data are presented both by theoretical consideration and the measurement of actual profiles of the well and threshold dependence on energy, dose, and drive-in conditions. Distributions of the electrical parameters are rather narrow with standard deviations of thresholds <150 mV. Transconductance constants are typically 9 and 29 µA . V^-2for p-and n-channel transistors, respectively. CMOS inverter gain is 250 for channel lengths of 10 and 25 µm, respectively.     

Channel ion implantation for small-geometry high-performance CMOS-SOS circuits

This paper describes an experimental study of channel ion implantation for optimization of small-geometry (1-1.5 µm) n- and p-channel silicon-on-sapphire (SOS) MOSFET's for high-performance CMOS applications. The influence of a wide range of channel implantation conditions on device characteristics are reported, and optimum channel doping profiles identified. Adequate performance of NMOS devices is achieved by the use of double boron channel implants, but excellent PMOS devices are obtained by the use of very lightly doped near-intrinsic device islands.     

High-accuracy physical modeling of submicrometer MOSFET's

When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.     

An n-channel MOSFET with Schottky source and drain

An n-channel MOSFET with Schottky source and drain (SBMOSFET) has been successfully fabricated using tantalum for the Schottky electrodes. For long gatelengths (100 µm), there are no significant differences in the characteristics of these SBMOSFET's compared to those of conventional MOSFET's. A significant current reduction is observed in SBMOSFET's having 10-µm gatelengths, however, due to the barrier between source and channel. In spite of the substantial barrier height (0.7 V) between tantalum and p-silicon, still larger barriers and a reduction in the isolation gap between source and channel are desirable for high-drive-high-speed device operation.     

A new VLSI memory cell using DMOS technology (DMOS cell)

A high-density dynamic memory cell using DMOS technology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing. Since n-DMOSFET threshold state is nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, which is made small by using two polysilicon layers and self-aligned structure, is about 50 percent of the conventional one-transistor memory cell area. An analytic model for DMOS cell readout voltage is proposed. From this model, the optimum DMOS cell structure, which gives more than 0.7-V readout voltage with 2-µm channel length, is found for 5-V power supply operation. Experimental data support this model. A 7-µA readout current per 1-µm channel width is obtained for 400-Å gate oxide test cell. The complete memory operation is confirmed with a 2 × 2 test cell array.     

Si MOSFET fabrication using focused ion beams

Submicrometer focused ion beams have been used both for the maskless ion implantation of p-channel depletion-mode Si MOSFET's and for the gate lithography of n-channel enhancement-mode Si MOSFET's. B-Pt and Au-Si liquid-metal-alloy ion sources were utilized in a single-lens focusing column for the implantation and lithography steps, respectively. An 800-Å-thick Al stopping layer was used at the target to separate the lighter ions from the heavier ion species in the beams. Reasonable dc electrical characteristics were measured for the chosen device process parameters.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFET's is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFET's.     

Silicon-on-insulator bipolar transistors

Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.     

A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n⁺and p⁺regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.     

Effects of mechanical strain on laser crystallized polysilicon thin film transistors and ring oscillators fabricated on stainless steel foil

In this paper the influence of mechanical tensile strain on the performance of thin film transistors (TFTs), with various channel geometries, and of ring oscillators, with 3, 7, 11, 21, and 51 number of stages and device channel lengths of 1, 4, and 8 μm, fabricated on stainless steel foil substrate is investigated. TFT parameters such as field effect mobility, threshold voltage, subthreshold slope, leakage and gate current for both n-channel, and p-channel TFTs are studied at various longitudinal tensile strain levels. For strain levels from 0.0% to 0.5%, the field effect mobility of n-channel TFTs increases while that of p-channel ones decreases as the longitudinal tensile strain increases. The field effect mobility, of both n-channel and p-channel TFTs, becomes independent of longitudinal tensile strain at strain levels greater than 0.5%. Threshold voltage and subthreshold slope of p-channel TFTs increases while that of n-channel ones does not follow a specific trend. The leakage current of both type devices tends to decrease by increasing the longitudinal tensile strain. The propagation delay, per inverter stage of a ring oscillator, is investigated at different supply voltages and tensile strain levels. The propagation delay of inverters with longer device channel length (?4 μm) tends to decrease while that of shorter length tends to increase as the longitudinal tensile strain increases.     

Very small MOSFET's for low-temperature operation

The improvements in the device characteristics of n-channel MOSFET's that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FET's with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.     

Experimental results on submicron-size p-channel MOSFET's

We report results on p-channel MOSFET's with channel lengths as small as 0.5 µm. Using design criteria obtained from numerical simulation, the devices have been fabricated by a low temperature process with very short annealing times. Fabricated devices with submicron channel lengths are dominated by velocity saturation of holes. Comparing the drive capability of n- and p-channel devices, we find the intrinsic device currents to be within a factor of 1.4 for a channel length of 0.5 µm.     

Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography

Subhalf-micrometer p-channel MOSFET's with ultra-thin gate oxide (3.5 nm) have been fabricated using X-ray lithography and electron cyclotron resonance (ECR) plasma etching. The fabricated MOSFET's with 0.2-µm channel lengths show long-channel behavior and extremely high (200 mS/mm) transconductance.     

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N⁺and P⁺diffusion and N⁺-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.