多晶硅发射极NPN管的辐射效应研究

为了研究多晶硅发射极双极晶体管的辐射可靠性,对多晶硅发射极NPN管进行了不同偏置条件下⁶⁰Co γ射线的高剂量率辐照试验和室温退火试验。试验结果表明,辐射后,基极电流IB显著增大,而集电极电流IC变化不大;反偏偏置条件下,IB的辐射损伤效应在辐射后更严重;室温退火后,IB有一定程度的持续损伤。多晶硅发射极NPN管与单晶硅发射极NPN管的辐射对比试验结果表明,多晶硅发射极NPN管的抗辐射性能较好。从器件结构和工艺条件方面,分析了多晶硅发射极NPN管的辐射损伤机理。分析了多晶硅发射极NPN管与单晶硅发射极NPN管的辐射损伤区别。     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

不同剂量率下NPN管和NMOSFET管的电离辐照效应

研究了 NPN双极晶体管和 NMOSFET在不同剂量率环境下的电离辐照效应。研究表明 ,NPN管在低剂量率辐照下 ,电流增益衰降更为显著 ,且具有真正的剂量率效应 ;而 NMOS管在低剂量率辐照下产生的阈电压负向漂移比高剂量率辐照时小 ,其辐照效应是时间相关效应 ,而非真正的剂量率效应。     

选择离子注入集电极技术研究

为提高超高速双极晶体管的电流增益 ,降低大电流下基区扩展效应对器件的影响 ,将选择离子注入集电区技术 (SIC)应用于双层多晶硅发射极晶体管中。扩展电阻的测试结果显示出注入的 P离子基本上集中在集电区的位置 ,对发射区和基区未造成显著影响。电学特性测量结果表明 ,经过离子注入的多晶硅发射极晶体管的电流增益和最大电流增益对应的集电极电流明显高于未经离子注入的晶体管。因此 ,在双层多晶硅晶体管中采用 SIC技术 ,有效地降低了基区的扩展效应 ,提高了器件的电学特性。     

低温大注入多晶硅发射极硅双极晶体管电流增益的定量模拟

已有的理论和实验都已证明，多晶硅发射极硅双极晶体管适合于低温工作，但至今为止，其完整的大注入时电流增益的理论分析还不成熟，特别是进行定量的计算。本文定量地模拟了低温７７Ｋ和常温３００Ｋ下多晶硅发射极硅双极晶体管电流增益与集电极电流密度的关系，并且分析了低温和常温下决定该晶体管电流增益大注入效应的主要物理效应。     

垂直发射极镇流电阻在HBT中的发射极电流集边效应中的作用

在异质结双极晶体管(HBT)功率器件中可以引入外延生长的发射极镇流电阻,以改善其热稳定性.通过理论计算和实验表明这种低掺杂的外延层不仅能作为镇流电阻,而且在功率HBT器件中还能非常有效地降低发射极电流集边效应.     

垂直发射极镇流电阻在HBT中的发射极电流集边效应中的作用

在异质结双极晶体管(HBT)功率器件中可以引入外延生长的发射极镇流电阻,以改善其热稳定性.通过理论计算和实验表明这种低掺杂的外延层不仅能作为镇流电阻,而且在功率HBT器件中还能非常有效地降低发射极电流集边效应.     

基于多晶外基区及SIC技术的高速NPN管设计

提出了一种先进的双多晶硅非自对准NPN管的器件结构,并实际用于一种高性能NPN管的研制.该器件结构主要通过多晶外基区减小基区电阻和基区结面积,以及使用SIC技术减小集电极电阻的方式,极大地提升了NPN管的特征频率.通过实际工艺流片验证,实现了BVCEO=5.6 V、fT=13.5 GHz的高速NPN管.该器件结构较双多晶自对准器件结构易于加工,可以广泛用于其他高速互补双极器件的研制.     

双极晶体管发射极电流集边效应理论及其在大生产中的应用研究

本文对双极晶体管发射极电流集边效应的理论研究作了回顾。文章指出：1971年,J.Olmstead等人在四个假设下,导出了一维的描述该效应的微分方程,并给出了它的近拟解。我们采用分离变量法,不作任何近似,导出了该微分方程的解析解,从而使描述该效应的理论得到了改进。该解析解理论应用于射频功率晶体管的版图设计中,取得明显效益。解析解不仅提高了描述该效应的精度,更重要的,是拓宽了理论适应的范围,从弱注入到极强注入的所有注入范围内,它都能适用,都能给出基区电位和发射极电流的分布函数。     

DPSA双极器件中的1/f噪声特性研究

在现代高性能模拟集成电路设计中,噪声水平是影响电路性能的关键因素之一。研究了双多晶自对准高速互补双极NPN器件中发射极结构对器件直流和低频噪声性能的影响。实验结果表明,多晶硅发射极与单晶硅界面超薄氧化层以及发射极几何结构是影响多晶硅发射极双极器件噪声性能的主要因素。     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Impact of fluorine incorporation in the polysilicon emitter of NPNbipolar transistors

We demonstrate that fluorine incorporation in the polysilicon emitter of NPN bipolar transistors significantly reduces the current gain h_fe. The gain degradation can be related to a reduction of the barrier to hole transport at the poly-Si/mono-Si interface. In addition to a gain reduction, fluorinated-emitter transistors display lower base recombination currents (at low base-emitter biases) than nonfluorinated emitter devices, suggesting that fluorine passivates recombination centers in the emitter-base space charge region     

Trade-off between emitter resistance and current gain inpolysilicon emitter bipolar transistors with intentionally growninterfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900°C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact     

超高速VLSI中多晶硅发射极晶体管串联电阻的测量

本文对目前流行的测量晶体管串联电阻的常规方法进行了理论分析和实验验证，结果表明，用常规方法测量多晶硅发射极晶体管串联电阻的误差很大。     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

Effect of emitter contact materials on high-performance verticalp-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements     

Extraction of emitter and base series resistances of bipolartransistors from a single DC measurement

A new procedure for extracting the emitter and base series resistances of bipolar junction transistors is presented. The parameters are extracted from a single measurement in the forward active region on one transistor test structure with two separate base contacts, making it a simple and attractive tool for bipolar transistor characterization. The procedure comprises two methods for extracting the emitter resistance and two for extracting the base resistance. The choice of method is governed by the amount of current crowding or conductivity modulation present in the intrinsic base region. The new extraction procedure was successfully applied to transistors fabricated in an in-house double polysilicon bipolar transistor process and a commercial 0.8-μm single polysilicon BiCMOS process. We found that the simulated and measured Gummel characteristics are in excellent agreement and the extracted series resistances agree well with those obtained by means of HF measurements. By adding external resistors to the emitter and base and then extracting the series resistances, we verified that the two base contact test structure offers a simple means of separating the influence of emitter and base series resistances on the transistor characteristics     

一种单层多晶硅BiCMOS工艺研究

介绍了一种单层多晶硅ＣＭＯＳ工艺。该工艺采用Ｐ型衬底,Ｎ型Ｐ型双埋层,Ｎ型薄外延结构,掺杂多晶硅作为ＣＭＯＳ晶体管栅极和双极ＮＰＮ晶体管的发射极。ＣＭＯＳ晶体管采用源漏自对准结构,钛和铝双层金属作为元件互连线,ＰＥＣＶＤＳｉＮｘ介质作为钝化薄膜。