1.47 /spl mu/m Tm/sup 3+/:ZBLAN fibre laser pumped at 1.064 /spl mu/m

A large core area (1257 /spl mu/m/sup 2/) Tm/sup 3+/-doped ZBLAN fibre laser operated at 1.47 /spl mu/m is demonstrated. The pump source is a Nd:YAG laser operated at 1.064 /spl mu/m. A laser output power of 1.56 W continuous wave was obtained for 5.2 W of launched pump power. The slope efficiency with respect to the launched pump power was measured to be 33%.     

Fibre-based source of femtosecond pulses tunable from 1.0 to 1.3 /spl mu/m

Tunable short-pulse generation in the spectral range 1030-1330 nm with an all-fibre source is demonstrated. A compact system with a femtosecond Yb fibre oscillator and a photonic crystal fibre relies on the soliton self-frequency shift to cover the wavelengths of primary interest to biological/biomedical imaging deep in tissue. Continuous tuning of <100 fs pulses with energies in the range 0.1-0.5 nJ is accomplished by adjusting the pulse energy.     

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process

Two fully integrated nMOS switches have been demonstrated at 15 GHz in a 0.13-/spl mu/m CMOS foundry process. One incorporates on-chip LC impedance transformation networks (ITNs) while the second one does not. The switches with and without ITNs achieve the same 1.8-dB insertion loss at 15 GHz, but 21.5 and 15 dBm input P/sub 1dB/, respectively. The degradation of insertion loss due to use of ITNs is compensated by reducing the mismatch loss caused by the bond pad parasitics. The switch without ITNs is suitable for 3.1-10.6 GHz ultra-wide-band (UWB) applications. The switch with ITNs has /spl sim/5 dB worse isolation than the switch without. The difference is due to the larger transistor size of the switch with ITNs, which introduces lower parasitic impedance path between Tx/Rx ports and antenna port.     

A fully integrated V-band PLL MMIC using 0.15-/spl mu/m GaAs pHEMT technology

A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-/spl mu/m GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35/spl times/1.80 mm/sup 2/. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip.     

A fully integrated 0.13-/spl mu/m CMOS mixed-signal SoC for DVD player applications

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications. It integrates one digital signal processor (DSP), two 32-bit CPUs, three dedicated processing units, a partial response maximum likelihood (PRML) read channel with an analog front end (AFE), and many other subsystems on the same die. The AFE includes a fifth-order G/sub m/-C filter and attains over 66 dB C/N overall. PR(3,4,4,3) structure is employed in the PRML read channel. Owing to the PRML signal processing and the mixed-signal system level optimization in the PRML read channel, less than 10/sup -6/ of bit-error rate (BER) is obtained for the focus offset margins over /spl plusmn/0.5 /spl mu/m. This SoC is fabricated in 0.13-/spl mu/m one-poly six-Cu CMOS technology. It contains 24 million transistors in a 63.87 mm/sup 2/ die and consumes 1.5 W at 40 MSample/s data rate, which corresponds to DVD 1.5 times playback operation mode.     

Quantum cascade lasers emitting at lambda greater than 100 /spl mu/m

Quantum-cascade lasers based on a bound-to-continuum transition and emitting at /spl lambda//spl sim/106 /spl mu/m (2.8 THz) are reported. They produce peak output powers of a few milliwatt and can be operated up to a heatsink temperature of 65 K. The devices demonstrate the feasibility of this technology for frequencies below 3 THz.     

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-/spl mu/m CMOS

A 2.1-GHz 1.3-V 5-mW fully integrated Q-enhancement LC bandpass biquad programmable in f/sub o/, Q, and peak gain is implemented in 0.35-/spl mu/m standard CMOS technology. The filter uses a resonator built with spiral inductors and inversion-mode pMOS capacitors that provide frequency tuning. The Q tuning is through an adjustable negative-conductance generator, whereas the peak gain is tuned through an input G/sub m/ stage. Noise and nonlinearity analyses presented demonstrate the design tradeoffs involved. Measured frequency tuning range around 2.1 GHz is 13%. Spiral inductors with Q/sub o/ of 2 at 2.1 GHz limit the spurious-free dynamic range (SFDR) at 31-34 dB within the frequency tuning range. Measurements show that the peak gain can be tuned within a range of around two octaves. The filter sinks 4 mA from a 1.3-V supply providing a Q of 40 at 2.19 GHz with a 1-dB compression point dynamic range of 35 dB. The circuit operates with supply voltages ranging from 1.2 to 3 V. The silicon area is 0.1 mm/sup 2/.     

Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-/spl mu/m CMOS

Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-/spl mu/m CMOS. This transceiver comprises full transmit and receive functions, including 1:16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UI/sub pp/ and transmitter jitter generation is 30 mUI/sub pp/. All functionality and specifications (core and I/O) are achieved with power dissipation of less than 1 W.     

A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-/spl mu/m CMOS

A low-power fully integrated synthesizer for Bluetooth applications is presented. The circuit with quadrature output signals at 2.45 GHz and 15-mW power dissipation has been designed in a digital 0.18-/spl mu/m CMOS process with 1.8-V supply voltage. The only external component is a 64-MHz crystal. Measurements have been performed on packaged samples mounted on an FR-4 board and show that the Bluetooth requirements are met. The measured phase noise is below -120 dBc/Hz at 3-MHz offset, and the resulting residual frequency modulation is 7.4-kHz rms. The tuning range consists of an analog and digital tuning mechanism, resulting in more than 15% overall tuning range.     

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-/spl Omega/ input and output matching is demonstrated in 0.18-/spl mu/m CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm/sup 2/.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

Optical amplification at 0.54 /spl mu/m by Tb/sup 3+/-doped fluoride fibre

0.54 mum band amplification using Tb³⁺-doped fluoride fibre is demonstrated. Spectroscopic properties of Tb³⁺-doped fluoride glass are clarified. A gain of 5.3 dB has been obtained in a 1 wt.% Tb³⁺-doped fluoride fibre for a signal power of -30 dBm by forward pumping at a wavelength of 0.488 mum with power of 100 mW     

Optical amplification at 0.54 /spl mu/m by Er/sup 3+/-doped fluoride fibre

Demonstrated is a 16.5 dB all-fibre optical amplifier at 546 nm using Er³⁺-doped fluoride fibre for a signal power of -30 dBm by forward upconversion pumping of a 974 nm laser diode. Results show Er ³⁺-doped fluoride fibre is a promising candidate for 0.54 mum optical amplifiers     

Singly Ho/sup 3+/-doped fluoride fibre laser operating at 2.92 /spl mu/m

A singly Ho/sup 3+/-doped fluoride fibre laser that uses energy transfer upconversion to maintain the population inversion has produced 340 mW at 2.92 /spl mu/m. The /spl sim/1100 nm output from a diode-cladding-pumped Yb/sup 3+/-doped silica fibre laser was used as the pump source and a maximum slope efficiency of 5% was obtained.     

A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS

This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply.     

Power scaling of 2 /spl mu/m ytterbium-sensitised thulium-doped silica fibre laser diode-pumped at 975 nm

An ytterbium-sensitised thulium-doped silica fibre laser that generates up to 75 W of output power in the 2 /spl mu/m wavelength range when cladding-pumped by a 975 nm diode stack is reported. The slope efficiency is 32% with respect to the launched pump power and the beam quality factor (M/sup 2/) is 1.3.     

1.53 /spl mu/m GaInNAsSb laser diodes grown on GaAs(100)

GaInNAsSb/GaNAs double quantum well ridge waveguide laser diodes with room temperature lasing wavelength of 1532 nm are reported. The devices exhibit leakage-corrected threshold current densities as low as 969 A cm/sup -2/ per quantum well in pulsed mode, with characteristic temperatures as high as 90 K.