AVS-P2、P7基于移动视频应用性能的比较

AVS是《信息技术先进音视频编码》系列标准的简称,是中国自主制定的音视频编码标准,主要面向高清晰度电视、高密度光存储和移动媒体等应用。它是一套包含系统、视频、音频、媒体版权管理在内的完整标准体系,其中视频标准包括两部分:面向数字电视应用领域的AVS-P2和面向移动应用领域的AVS-P7。针对AVS两种视频标准基于移动视频应用领域上的关键技术进行比较,通过实验数据进行分析;对两种视频标准在移动视频领域的应用前景进行探讨。     

AVS—P2、P7基于移动视频应用性能的比较

AVS是<信息技术先进音视频编码>系列标准的简称,是中国自主制定的音视频编码标准,主要面向高清晰度电视、高密度光存储和移动媒体等应用.它是一套包含系统、视频、音频、媒体版权管理在内的完整标准体系,其中视频标准包括两部分:面向数字电视应用领域的AVS-P2和面向移动应用领域的AVS-P7.针对AVS两种视频标准基于移动视频应用领域上的关键技术进行比较,通过实验数据进行分析;对两种视频标准在移动视频领域的应用前景进行探讨.     

AVS-P10音频解码器算法分析与定点化

AVS-P10是我国第一部应用于移动环境的音频编解码国家标准。在分析AVS-P10解码算法的基础上,对参考代码进行了精简和封装。针对定点处理器应用需求,对精简后的代码进行了定点化实现和优化。分别采用CMOS评分与SNR指标,对定点解码器的解码质量进行了主、客观测试,并对优化前后的定点解码器的运算效率进行了比对测试。结果表明,提出的AVS-P10定点解码器的解码音质达到与浮点解码信号的音质相当,且运算复杂度明显下降。     

H.264到AVS快速视频转码技术研究

通过深入对比和分析H.264 Main Profile和AVS-P2的L4.2两种视频编解码标准,本文提出一种快速实现H.264到AVS视频转码的技术,并对该转码技术进行软件实现。     

基于软硬件分区的AVS高清视频解码器结构

硬件的强大处理能力及软件的灵活性和可编程性,使得视频解码芯片的结构从硬件转向软硬件分区结构.作为新兴的标准,AVS视频标准对解码器的软硬件分区结构提出新的挑战.从AVS视频标准算法和实现复杂度入手,提出一种AVS高清视频解码器软硬件分区结构,实现满足基准档次6.0级别的AVS高清视频码流的实时解码,支持灵活的音视频同步、错误恢复、缓冲区管理和系统控制机制.已经在AVS101芯片上实现,硬件采用7阶宏块级同步流水,软件任务在RISC处理器上实现,可以在148.5MHz工作频率下对NTSC,PAL,720p(60f/s),直至1080i(60field/s)节目的实时解码显示.     

AVS标准中的视频编码关键技术研究

AVS是中国自主制定的数字音视频编码系列标准,主要研究了AVS-P2和AVS-P7中的关键技术,并与国际上最新视频压缩标准H.264/AVC中的关键技术进行对比分析.最后介绍了AVS工作组的最新进展,分析了AVS的产业化现状和应用前景.     

基于FPGA的AVS帧内预测的研究与设计

本文通过对AVS视频标准中帧内预测算法的研究,提出了一种新的基于FPGA的AVS解码器帧内预测模块的设计方案。文中设计的通用运算单元,提高了硬件资源的可重构性,降低了帧内预测的计算复杂度。设计中采取有效的控制逻辑,对复杂的plane模式进行预处理,提高了预测速度。上述设计已通过RTL级综合及仿真,并在结合AVS参考模型RM52j和ver-ilog语言的DPI接口建立的验证平台上,验证了该模块功能的正确性。     

基于AVS-P7标准插值计算模块的VLSI实现

AVS-P7(即AVS-M)是AVS系列标准中的第七部分移动视频编码标准.提出一种基于AVS-P7运动补偿单元的VLSI结构,采用改进的片上RAM读写机制和插值计算单元结构,以较少内存访问次数和较低的硬件代价,满足SD数据流实时解码的要求.     

基于混沌的AVS视频压缩加密算法

针对AVS的编码结构,提出一种基于混沌理论的AVS视频加密算法,并集成到AVS编/解码器中。该算法采用实值混沌序列加密和置乱DCT非零系数来加密视频信息。采用3个标准视频序列进行算法仿真,在为AVS编写的rm52j软件平台上进行实验,结果表明,该算法加密速度快,安全性高,对压缩比影响较少。     

AVS 3D实时解码器在FPGA/SoC平台上的设计与实现

AVS(audio video coding standard)工作组针对3D视频提出了双目立体视频编解码方案。以AVS双目拼接算法为核心,通过FPGA硬件加速模块完成双目立体ES流的语法元素解析,与So C开发板Xilinx ZYNQ 7020协同工作,创新性地在FPGA/So C协同平台上实现了AVS 3D实时解码器。通过HDMI接口将解码数据输出到三维显示设备,得到了具有深度信息的3D视频,验证了AVS 3D实时解码器的有效性。     

An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder

In the part 2 of advanced Audio Video coding Standard （AVS-P2）, many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, symmetric matching, quarter precision interpolation, etc. However, these new features enormously increase the computational complexity and the memory bandwidth requirement, which make motion compensation a difficult component in the implementation of the AVS HDTV decoder. This paper proposes an efficient motion compensation architecture for AVS-P2 video standard up to the Level 6.2 of the Jizhun Profile. It has a macroblock-level pipelined structure which consists of MV predictor unit, reference fetch unit and pixel interpolation unit. The proposed architecture exploits the parallelism in the AVS motion compensation algorithm to accelerate the speed of operations and uses the dedicated design to optimize the memory access. And it has been integrated in a prototype chip which is fabricated with TSMC 0.18-#m CMOS technology, and the experimental results show that this architecture can achieve the real time AVS-P2 decoding for the HDTV 1080i （1920 - 1088 4 ： 2 ： 0 60field/s） video. The efficient design can work at the frequency of 148.5MHz and the total gate count is about 225K.     

AVS及H.264双模可变长解码器设计

为使视频解码芯片能同时兼容AVS及H.264这2种视频编码标准,设计一种双模可变长解码器。该设计复用码流缓冲移位和指数哥伦布解码模块,采用组合逻辑电路查找码表,对AVS和H.264码表进行优化与重组。在ModelSim环境下完成仿真测试,并通过FPGA芯片进行综合验证。结果表明,该设计能有效支持AVS和H.264 2种标准,减小电路资源消耗和面积,并提高查找表的查找效率。     

基于AVS-P2的自适应时空域错误隐藏方法

错误隐藏技术是视频传输中保证重建质量的重要技术,可以有效恢复传输过程中因传输环境恶劣等原因造成的信息丢失和错误,为了增强AVS-P2的抗传输差错能力,提出了一种基于冗余运动矢量的自适应时空域错误隐藏算法。对I帧中的受损宏块采用空域错误隐藏方法,利用受损宏块周围已正确解码像素值进行加权插值来恢复;而对非I帧中的受损宏块则采用时域错误隐藏方法,根据宏块的运动剧烈程度分别选择AVS-P2中通用的错误隐藏方法和基于冗余运动矢量的错误隐藏方法。最后,在AVS-P2 RM52_20080721平台上实现了该算法,大量仿真实验结果表明,所提方法相比原有方法,解码视频图像的客观质量和主观效果均得到了一定提升。因此,所提方法可以有效保证AVS-P2解码端接收视频的主观质量,增强了其抗传输差错能力。     

基于TMS320DM6446的AVS—P2编码器的开发及优化

介绍了AVS—P2视频编码关键技术和数字多媒体开发平台TMS320DM6446的结构特点,研究了在该DSP上对AVS—P2视频编码器的移植和优化,取得良好效果。     

On2解码器的优化及其在嵌入式平台上的实现

首先介绍了On2 VP6视频解码器的原理,对其复杂度进行了分析,然后对IDCT(inverse discrete cosine transform)、颜色空间转换等解码器中最耗时的两个模块进行了算法优化.接下来,结合裕兴公司机顶盒YX-5911A平台的特点,对VP6解码器进行了汇编级的优化.测试结果表明,对于CIF格式的视频,在实现VP6视频解码、显示播放的情况下,优化后的VP6视频解码达到了12 f/s以上的解码速度,基本满足实时解码播放的要求.     

Network-driven low complexity coding for wireless multi-view video system

For wireless multi-view video system, which has very limited capability for storage and computation at the encoder, it is essential to design a video coding scheme with low complexity. Wyner-Ziv (WZ) coding scheme shifts large computational complexities to decoder with side information reconstruction, however, its encoding efficiency is not high enough. To obtain higher encoding efficiency and lower encoding complexity for wireless multi-view video applications, a network-driven low complexity video coding method is proposed in the paper. The proposed method is designed to implement color correction, motion vector extrapolation and disparity extraction at the central node of network, so as to reduce large computational complexities of motion estimation at the encoder and disparity estimation at the decoder. Experimental results show that encoding efficiency of the proposed method is higher than those of WZ coding and H.264 intraframe coding methods. The encoding complexity of the proposed method is greatly decreased and the decoded views are of color consistency, which is favorable to high quality view rendering at the decoder.     

Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine

In this paper, a low-cost compatible motion compensator is implemented and integrated into a macroblock-level three-stage-pipelined HDTV decoder, in which an embedded compression (EC) engine is realized as well. The decoder with EC engine is designed to reduce the power consumption and memory bandwidth requirement since memory accesses are reduced. In the motion compensator, a boundary judgment scheme for reference pixel fetching is proposed to provide seamless integration in HDTV video decoder for the block-based EC engines. Furthermore, a buffer sharing mechanism is adopted to reduce extra memory requirement involved by EC. The reference pixel fetching unit costs only 17.3 K logic gates when the working frequency is set to 166.7 MHz. On average, when decoding HD1080 video sequence, 30% memory access reduction and 24% memory power consumption saving are achieved when a near lossless EC algorithm is integrated in the video decoder. In other words, the proposed motion compensator makes the EC engine an integral part of a memory reduced decoder without extra cost. Additionally, since the work in this paper is based on EC schemes, the EC design criterion are discussed, and several useful rules on the selection of EC algorithm are addressed for the video decoder of corresponding VLSI architecture.