共查询到14条相似文献，搜索用时 62 毫秒
1.
通过运用Si3N4和SiO2作掩膜,采用各向同性和各向异性腐蚀液,利用硅的腐蚀自停止特性,实现了硅梁的纳米宽度控制,同时利用多次氧化在SOI材料上实现了纳米厚度控制,最终成功批量制作了硅纳米线.扫描电镜观测表明,制备的纳米线厚度和宽度都可严格控制在100nm以下,最细的纳米线宽度可以达到20nm.同批样品的宽度变化范围在20%以内.大气中对其电学特性测量表明,剥离了表面氧化层的纳米线的电阻会随放置时间的增长而逐渐增大.进一步实验分析发现水分吸附在其电阻变化中起了重要的作用. 相似文献
2.
通过运用Si3N4和SiO2作掩膜,采用各向同性和各向异性腐蚀液,利用硅的腐蚀自停止特性,实现了硅梁的纳米宽度控制,同时利用多次氧化在SOI材料上实现了纳米厚度控制,最终成功批量制作了硅纳米线.扫描电镜观测表明,制备的纳米线厚度和宽度都可严格控制在100nm以下,最细的纳米线宽度可以达到20nm.同批样品的宽度变化范围在20%以内.大气中对其电学特性测量表明,剥离了表面氧化层的纳米线的电阻会随放置时间的增长而逐渐增大.进一步实验分析发现水分吸附在其电阻变化中起了重要的作用. 相似文献
3.
将非金属元素碘作为硅的KOH腐蚀液的添加物,在对(100)和(110)单晶硅片的各向异性腐蚀中,获得了更为丰富的异向腐蚀特性和更为光滑的腐蚀表面。当温度在95℃,KOH腐蚀液中碘的摩尔比为0.5时,得到了粗糙度均小于10nm的Si-(100)和(110)光洁表面,两晶面的腐蚀速率均为1.4μm/min。这两晶面在相同的条件下同时达到最佳光洁度,说明腐蚀速率是获得高光洁度表面的关键。实验还证明碘在热碱溶液中的稳定性和持久性要高于现在已被大量研究的双氧水和过硫等,尤其是对硅(110)表面光洁度的改善具有积极的促进作用。 相似文献
4.
赵忆王家畴陈方李昕欣 《微纳电子技术》2015,(6):390-395
介绍了一种新型单片集成电容式三轴微加速度计的加工方法,该方法采用非绝缘体上硅(SOI)的单硅片单面加工技术,易于与IC工艺兼容,而且成本低廉,成品率高,适用于批量生产,可替代传统的SOI工艺。该方法主要利用硅深度反应离子刻蚀(DRIE)技术结合普通(111)单晶硅片内部可选择性横向自停止腐蚀技术制作并释放得到悬浮可动的敏感结构。此外,创新的锚点设计不仅使检测电极之间相互电学隔离,而且便于引线键合与封装。最后基于开环接口电路对加工制造的三轴加速度计进行了测试,验证了该工艺的可行性。 相似文献
5.
Nanoscale refinement on a(100) oriented silicon-on-insulator(SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide(TMAH,25 wt%) anisotropic silicon etchant,with temperature kept at 50℃to achieve precise etching of the(111) crystal plane.Specifically for a silicon nanowire(SiNW) with oxide sidewall protection,the in situ TMAH process enabled effective size reduction in both lateral(2.3 nm/min) and vertical (1.7 nm/min) dimensions.A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly,yielding enhanced field effect transistor(FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart,which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality ofthe(111) plane,as well as the bulk depletion property should be the causes of this electrical enhancement,which implies the great potential of the as-made cost-effective SiNW FET device in many fields. 相似文献
6.
硅各向异性浅槽腐蚀实验研究 总被引：1，自引：0，他引：1
通过实验分析,对比了异丙醇(IPA)和超声波对Si(100)面在KOH溶液和四甲基氢氧化氨(TMAH)溶液中的浅槽腐蚀速率及其表面形态的影响。实验结果表明,IPA能降低TMAH溶液的腐蚀速率,但IPA在KOH溶液中腐蚀速率降低不明显;IPA加入到较高浓度的KOH溶液中,会在Si表面产生较大小丘,恶化了Si腐蚀表面的质量,但在TMAH溶液中加入一定量的IPA会改善腐蚀表面的质量;超声波能加快腐蚀速率并能改善Si腐蚀表面质量,但对于加入IPA的较高浓度KOH溶液,超声波未能消除Si腐蚀表面的小丘,另外,超声波还能减弱腐蚀过程中微尺寸沟槽的尺寸效应;在腐蚀条件和配比一定情况下,TMAH溶液的腐蚀质量比KOH溶液好。 相似文献
7.
Jiansheng Jie Wenjun Zhang Kuiqing Peng Guodong Yuan Chun Sing Lee Shuit‐Tong Lee 《Advanced functional materials》2008,18(20):3251-3257
Surface effects are widely recognized to significantly influence the properties of nanostructures, although the detailed mechanisms are rarely studied and unclear. Herein we report for the first time a quantitative evaluation of the surface‐related contributions to transport properties in nanostructures by using Si nanowires (NWs) as a paradigm. Critical to this study is the capability of synthesizing SiNWs with predetermined conduction type and carrier concentration from Si wafer of known properties using the recently developed metal‐catalyzed chemical etching method. Strikingly, the conductance of p‐type SiNWs is substantively larger in air than that of the original wafer, is sensitive to humidity and volatile gases, and thinner wires show higher conductivity. Further, SiNW‐based field‐effect transistors (FETs) show NWs to have a hole concentration two orders of magnitude higher than the original wafer. In vacuum, the conductivity of SiNWs dramatically decreases, whereas hole mobility increases. The device performances are further improved by embedding SiNW FETs in 250 nm SiO2, which insulates the devices from atmosphere and passivates the surface defects of NWs. Owing to the strong surface effects, n‐type SiNWs even change to exhibit p‐type characteristics. The totality of the results provides definitive confirmation that the electrical characteristics of SiNWs are dominated by surface states. A model based on surface band bending and carrier scattering caused by surface states is proposed to interpret experimental results. The phenomenon of surface‐dependent transport properties should be generic to all nanoscale structures, and is significant for nanodevice design for sensor and electronic applications. 相似文献
8.
This work introduces and explores vapor phase metal‐assisted chemical etching (VP‐MaCE) of silicon as a method to bypass some of the challenges found in traditional liquid phase metal‐assisted chemical etching (LP‐MaCE). Average etch rates for Ag, Au, and Pd/Au catalysts are established at 31, 70, and 96 nm/min respectively, and the relationship between etch rate and substrate temperature is examined experimentally. Just as with LP‐MaCE, 3D catalyst motion is maintained and three‐dimensional structures are fabricated with nanoparticle‐ and lithography‐patterned catalysts. VP‐MaCE produces less microporous silicon compared with LP‐MaCE and the diffusion/reduction distance of Ag+ ions is significantly reduced. This process sacrifices etch rate for increased etch uniformity and lower stiction for applications in micro‐electromechanical systems (MEMS) processing. 相似文献
9.
10.
Pinned structures in conjunction with shaped catalysts are used in metal‐assisted chemical etching (MACE) of silicon to induce out‐of‐plane rotational etching. Sub‐micro‐ and nanostructures are fabricated in silicon, which include scooped‐out channels and curved subsurface horns, along with vertically oriented thin metal structures. Five different etching modes induced by catalyst and pinning geometry are identified: 1) fully pinned–no etching, 2) rotation via twist, 3) rotation via delamination, 4) in‐plane bending, and 5) swinging. The rotation angle is roughly controlled through catalyst geometry. The force and pressure experienced by the catalyst are calculated from the deformation of the catalyst and range between 0.5–3.5 μN and 0.5–3.9 MPa, respectively. This is a new, simple method to fabricate 3D, heterogeneous sub‐micro‐ and nanostructures in silicon with high feature fidelity on the order of tens of nanometers while providing a method to measure the forces responsible for catalyst motion during MACE. 相似文献
11.
Taeho Moon Lin Chen Shinhyun Choi Chunjoong Kim Wei Lu 《Advanced functional materials》2014,24(13):1949-1955
Nanowires (NWs) have shown great potential for applications in flexible and transparent electronics. The main challenges lie in improving the transfer yield and reducing the cost of NW fabrication. Here, it is shown that a bilayer SiNW structure can spontaneously form during metal‐assisted chemical etching (MaCE). The bilayer structure formation is in turn accompanied by horizontal weak point formation that facilitates efficient nanowire transfer to diverse substrates. A mass‐transport model is developed to explain the bilayer structure and horizontal crack formation effects. Significantly, these results allow repeated SiNW etch/transfer from the same Si wafer, thus potentially greatly reducing the fabrication cost of NW‐based electronics. SiNW array‐based transistors fabricated from two sequential etch/transfer processes using a single wafer are successfully demonstrated on Si and plastic substrates. 相似文献
12.
TMAH单晶硅腐蚀特性研究 总被引：7，自引：1，他引：7
TMAH是一种具有优良的腐蚀性能的各向异性腐蚀剂,选择性好,无毒且不污染环境,最重要的是TMAH与CMOS工艺相兼容,符合SOC的发展趋势。TMAH正逐渐替代KOH和其他腐蚀液,成为实现MEMS工艺中微三维结构的主要腐蚀剂。本文着重介绍了TMAH的特性、工艺条件及应用。 相似文献
13.
We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits. 相似文献
14.
For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET. 相似文献