基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

一种适用于低压高速嵌入式应用的2T P沟道纳米晶存储器件

本文基于嵌入式应用的低压、高速要求,提出了一种基于2T结构的P沟道纳米晶存储新型结构。该器件采用带带隧穿激发热电子注入(BTBTIHE)的编程方式,可以同时实现高速、低功耗编程。同时采用2T结构以简化外围高压和读出电路。该器件具有良好的存储特性,包括高编程速度（5us编程脉冲下获得1.1V窗口）和优异的数据保持特性（在10年的保持时间电荷损失仅为20%）。该器件在嵌入式非挥发存储领域具有很强的应用潜力。     

SONOS存储单元数据保持特性退化研究

探讨了基于Fowler-Nordheim(F-N)隧穿进行编程、擦除的硅-氧化物-氮化物-氧化物-硅(SONOS)存储单元在擦写循环后的数据保持特性。分别通过分析和实验研究了擦写过程中操作电压大小对于VTH(编程)态、VTL(擦除)态存储单元数据保持性能退化的影响。对于VTH态单元,其数据保持性能退化程度受操作电压大小的影响不明显,电荷流失速度主要受温度影响；而VTL态单元数据保持性能退化程度受操作电压大小的影响较大,电荷流失速度与温度的关系不明显。通过对比不同操作条件下进行擦写循环后的数据保持性能退化程度,总结了有利于减小SONOS存储器数据保持性能退化的操作条件。     

华虹NEC成功开发具超高可靠性的嵌入式非挥发性存储器模块

上海华虹NEC电子有限公叫近LI宣布,基于公司成熟的0．13微米SONOS嵌入式仔储器T艺平台,已成功地开发Ⅲ了具有趟高可靠性（UHR—ultraHighReliability）的嵌入式非挥发性存储器模块（EEPROM／FlashlP）,使0．13微米SONOSEEPROM／FlashIP的数据保存时问从常规的10年提升到了超过30年,而擦写次数则从100K大幅提高到超过500K。这次在0．13微米嵌入式存储器工艺上的技术提升将进一步扩大华虹NEC在嵌入式非挥发性存储器代工市场上的竞争优势,巩固公司在智能卡和安全类芯片领域的地位。（来自华虹NEC）     

银纳米线对光驱动液晶显示器擦写时间的影响

光驱动液晶显示器（Optically Driving Liquid Crystal Display,ODLCD）是通过利用目标光轴排列以线偏振信息的形式写入光取向层,进而引导液晶微区取向技术的一种新型液晶显示器。ODLCD不仅具有功耗低的显著性优点,而且可以利用偏振光对信息进行擦除和改写。但由于目前ODLCD存在擦写时间较长这一缺点,限制了其在实际中的应用。为了降低ODLCD的擦写时间,本文通过在液晶中掺入液晶单体RM257和银纳米线（AgNWs）并在电场下发生光交联,探究了不同浓度（质量分数）RM257和AgNWs对ODLCD擦写时间的影响。实验结果表明,RM257和AgNWs都对ODLCD的擦写时间有着较显著的影响,在RM257浓度为12%和AgNWs浓度为1%时,ODLCD的擦写时间较短。该研究改善了ODLCD的擦写时间性能,对其在实际中的应用具有一定的研究价值。     

10MHz高速32kb SPI串行EEPROM

Mieroehip Technology Ine．（美国微芯科技公司）推出25AA320A和25LC320A（25XX320A）器件以扩展其32kbSPI串行EEPROM系列。新器件的速度可达10MHz。 25XX320A具有快捷的字节级和页面级擦写功能以及快速的数据存取时间。这些器件以Microehip专有的PMOS电可擦除单元（PEEC）架构为基础，使高密度器件可置于小巧封装内。并保持高度耐用性（100万次擦除，写入）及业界领先的保存时间（200年）；同时能在汽车应用等高温的恶劣环境中高速运行。     

FLASH存储单元擦写过程中的电流分析

文章将讨论不挥发存储器单元－ＦＬＡＳＨ的擦写过程，包括对擦写原理的描述重点其擦写过程的电流进行分析，建立了适用于该单元的电流模型，并结合本所工艺线的实验单元进行测试，在对建立的模型和理论进行验证。     

铁电存储器FM1808

铁电存储器是Ramtron公司近年来推出的一款掉电不挥发存储器，它结合了高性能和低功耗的操作，能在没有电源的情况下保存数据。FRAM克服了EEPROM和Flash写入时间长、擦写次数少的缺点。其价格又比相同容量的不挥发锂电SRAM低很多。已在工控仪表、办公复印机、高档服务器等系统中应用，具有广阔的应用前景。     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

THS320C5402在线擦写F1ash实现自举加载

本文介绍了用TMS320C5402在线擦写Flash芯片的方法。硬件电路选用DRAM芯片IS61LV25616AL（256K×16bits）作为片外程序存储器，以提高程序运行速度，用FLASH芯片AT29LV1024（64K×16bits）作为片外数据存储器来实现Bootload，使TMS320C5402芯片能独立运行；软件设计用DSP汇编语言来编写擦写程序，并给出了参考程序。     

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory(NVM) are investigated. A good performance of the memory cell has been achieved,including a fast program/erase(P/E) speed under low voltages,an excellent data retention(maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10%after 10~4 P/E cycles.The data show that the device has strong potential for future embedded NVM applications.     

Low-voltage programmable/erasable high performance flexible organic transistor nonvolatile memory based on a tetratetracontane passivated ferroelectric terpolymer

Future flexible electronic systems require memory devices combining low power consumption and mechanical bendability. However, high programming/erasing (P/E) voltages, which are universally required to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a novel route to achieve a low-voltage programmable/erasable flexible Fe-OFET NVM. Ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)], rather than the conventional ferroelectric copolymer poly(vinylidene-fluoride-trifluoroethylene) [P(VDF-TrFE)], is used as the gate dielectric. The low coercive field of P(VDF-TrFE-CTFE) is the main contribution to the low-voltage operation in the Fe-OFET NVM, even with a relative thick ferroelectric gate dielectric layer. By depositing a long-chain alkane molecule Tetratetracontane (TTC) as the passivation layer on the surface of P(VDF-TrFE-CTFE) film, the layer-by-layer growth mode of semiconductor pentacene is obtained, which results in a large crystalline grain and good interface morphology at the channel/dielectric. Therefore, the mobility of Fe-OFET NVMs is greatly improved. As a result, a high performance flexible Fe-OFET NVM is achieved, with a low P/E voltage of ±15 V, high mobility up to 0.5 cm² V⁻¹ s⁻¹, reliable P/E endurance property over 1000 cycles, stable data storage retention capability over 6000 s, and excellent mechanical bending durability without visible degradation after 2000 repetitive tensile bending cycles at a small curvature radius of 4.0 mm.     

Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10⁻¹¹ A, for the TFT without an offset region, to the low OFF current of 1.34 × 10⁻¹² A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10⁻⁶ S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.     

Indium-tin-oxide,free, flexible,nonvolatile memory devices based on graphene quantum dots sandwiched between polymethylsilsesquioxane layers

Indium-tin-oxide (ITO) free, nonvolatile memory (NVM) devices based on graphene quantum dots (GQDs) sandwiched between polymethylsilsesquioxane (PMSSQ) layers were fabricated directly on polyethylene terephthalate (PET) substrates by using a solution process technique. Current-voltage (I-V) curves for the silver nanowire/PMSSQ/GQD/PMSSQ/poly(3,4-ethylenethiophene):poly(styrene sulfonate)/PET devices at 300 K showed a current bistability. The ON/OFF ratio of the current bistability for the NVM devices was as large as 1 × 10⁴, and the cycling endurance time of the ON/OFF switching for the NVM devices was above 1 × 10⁴ s. The Schottky emission, Poole-Frenkel emission, trapped-charge limited-current, and space-charge-limited current were dominantly attributed to the conduction mechanisms for the fabricated NVM devices based on the obtained I-V characteristics, and energy band diagrams illustrating the “writing” and the “erasing” processes of the devices.     

Fully depleted double-gate MSDRAM cell with additional nonvolatile functionality

We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in non-volatile memory (NVM) mode. The NVM functionality is achieved by Fowler–Nordheim tunneling hole injection into the nitride storage node; the injected holes induce a permanent inversion layer in silicon body. The proposed device shows a large current ratio between ‘1’ and ‘0’ states (～10³) and a wide memory window (～3 V). The effect of the NVM functionality on the MSD hysteresis was investigated and combined with the effect of the control-gate bias. The SONOS charging can be used for replacing the second gate (i.e. enabling single-gate MSDRAM) or for achieving ‘unified’ memory operation.     

Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.     

Tristable switching of the electrical conductivity through graphene quantum dots sandwiched in multi-stacked poly(methyl methacrylate) layers

Tristable switching nonvolatile memory (NVM) devices based on graphene quantum dots (GQDs) sandwiched between multi-stacked poly (methyl methacrylate) (PMMA) layers were fabricated on indium-tin-oxide (ITO)-coated glass substrates by using a solution-processed method. Current-voltage (I-V) curves at 300 K for the silver nanowire/PMMA/GQD/PMMA/GQD/PMMA/ITO/glass devices showed tristable switching currents with high-resistance, intermediate-resistance, and low-resistance states. The device's cycling endurance of the three resistance states remained stable with a distinguishable value for each resistance state over 1000 cycles, and the obtained retention results showed well-distinguished resistance states without degradation for up to 1 × 10⁴ s. Schottky emission, Poole-Frenkel emission, trapped-charge limited-current, and ohmic conduction were proposed as the dominant conduction mechanisms for the fabricated NVM devices based on the obtained I-V characteristics. The described energy-band diagrams confirm the proposed conduction band mechanisms.     

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.     

System-level impacts of persistent main memory using a search engine

Computer memory systems traditionally use distinct technologies for different hierarchy levels, typically volatile, high speed, high cost/byte solid state memory for caches and main memory (SRAM and DRAM), and non-volatile, low speed, low cost/byte technologies (magnetic disks and flash) for secondary storage. Currently, non-volatile memory (NVM) technologies are emerging and may substantially change the landscape of memory systems. In this work we assess system-level latency and energy impacts of a computer with persistent main memory using PCRAM and Memristor, comparing the development and execution of a search engine application implementing both a traditional file-based approach and a memory persistence approach (Mnemosyne). Our observations show that using memory persistence on top of NVM main memory, instead of a file-based approach on top DRAM/Disk, produces less than half lines of code, is more than 4× faster to develop, consumes 33× less memory energy, and executes search tasks up to 33× faster.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.