具有浮空埋层的高压器件新结构和击穿电压模型

提出具有浮空埋层的变掺杂高压器件新结构(BVLD:Variation in lateral doping with floating buriedlayer),建立其击穿电压模型.线性变掺杂漂移区的电场耦合作用使表面电场达到近似理想的均匀分布,n+浮空等电位层与衬底形成新平行平面结,使得纵向电压由常规结构的一个pn结承...     

单个浮置场限环终端结构击穿电压模型

基于B.J.Baliga的击穿电压理论,通过求解双边突变圆柱结的泊松方程,提出了单个浮置场限环终端结构的击穿电压解析模型.该模型计算结果与模拟结果的误差在±7%之内,具有精度高、应用范围广等特点,可以帮助设计者初步确定浮置场限环注入窗口大小及与主结的间距等关键参数.     

衬底偏压对硅基高压器件新结构击穿电压特性的影响

提出基于衬底偏压技术的double RESURF结构,称为Sb double RESURF LDMOS。在n型衬底和n型漂移区之间嵌入p型外延层,阻挡器件阻断状态下的纵向电流通路,改变体内电场分布。衬底偏压加强漂移区电荷共享效应,降低漏极下方纵向电场峰,该技术对提高薄漂移区横向功率器件的纵向击穿电压尤其重要。结果表明,在保持较小导通电阻下,该结构较常规LDMOS击穿电压提高97%。     

带N型浮空岛的新型LDMOS

为了解决薄外延横向功率器件的纵向耐压问题,提出了一种带有N型浮空岛的新型LDMOS。与传统LDMOS不同,该结构在漏端下方的衬底耗尽层内加入多个纵向排列的N型浮空岛,扩展了衬底的耗尽层,降低了漏端下方的高电场,在纵向引入新的峰值电场,优化了器件的横向和纵向电场分布,大幅提高了器件的击穿电压。利用Sentaurus TCAD软件对新结构进行了仿真。结果表明,漂移区长度均为80 μm时,新结构的击穿电压为964 V,比相同漂移区长度下的传统LDMOS提高了113.7%,优值为1.01 MW·cm-2,比传统LDMOS提高了211%。     

浮空层结构的分析

分析了REBULF LDMOS的实验结果，由击穿电压的测试结果验证了模拟仿真中发现的漏电流增加源于n+浮空层的作用，但暴露于表面的n+p结的漏电流使击穿电压降低. 为了解决这个问题，文中分析了具有部分n+浮空层的REBULF LDMOS结构，此结构不但具有降低体内电场的REBULF效应，而且终止于源端体内的n+p结解决了文献［10］中的大漏电流问题. 分析结果表明，击穿电压较一般RESURF LDMOS结构提高60%以上.     

埋层低掺杂漏SOI高压器件的击穿电压

提出一种具有埋层低掺杂漏(BLD)SOI高压器件新结构。其机理是埋层附加电场调制耐压层电场,使漂移区电荷共享效应增强,降低沟道边缘电场,在漂移区中部产生新的电场峰。埋层电中性作用增加漂移区优化掺杂浓度,导通电阻降低;低掺杂漏区在漏极附近形成缓冲层,改善漏极击穿特性。借助二维半导体仿真器MEDICI,研究漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在器件参数优化理论的指导下,成功研制了700V的SOI高压器件。结果表明:BLD SOI结构击穿电压由均匀漂移区器件的204V提高到275V,比导通电阻下降25%。     

单场限环的平面高压器件

通过优化设计和充分利用硅片面积 ,研制出了场限环的平面高压半导体分立器件     

SBFL结构SiGe HBT器件的击穿特性研究

对高频SiGe HBT器件的击穿特性进行了研究。借助TCAD仿真工具,对超结结构引入器件集电区后的击穿特性进行了分析,提出了一种采用分裂浮空埋层结构(SBFL)的SiGe异质结器件。这种结构改善了器件的内部电场分布,电场分布由原来的单三角形分布变成双三角形分布。仿真结果表明,该器件结构的击穿电压由原有的3.6 V提高到5.4 V,提高了50%。     

薄型双漂移区高压器件新结构的耐压分析

提出与CMOS工艺兼容的薄型双漂移区(TD)高压器件新结构.通过表面注入掺杂浓度较高的N-薄层,形成不同电阻率的双漂移区结构,改变漂移区电流线分布,降低导通电阻;沟道区下方采用P离子注入埋层来减小沟道区等位线曲率,在表面引入新的电场峰,改善横向表面电场分布,提高器件击穿电压.结果表明:TD LDMOS较常规结构击穿电压提高16%,导通电阻下降31%.     

单场限环的平面高压器件

通过优化设计和充分利用硅片面积，研制出了场限环的平面高压半导体分立器件。     

A novel high-voltage device structure with an N~+ ring in substrate and the breakdown voltage model

A novel high-voltage device structure with a floating heavily doped N~+ ring embedded in the substrate is reported,which is called FR LDMOS.When the N~+ ring is introduced in the device substrate,the electric field peak of the main junction is reduced due to the transfer of the voltage from the main junction to the N~+ ring junction, and the vertical breakdown characteristic is improved significantly.Based on the Poisson equation of cylindrical coordinates,a breakdown voltage model is developed.The numerical results indicate that the breakdown voltage of the proposed device is increased by 56%in comparison to conventional LDMOS.     

An analytical model for punch-through limited breakdown voltage of planar junction with multiple floating field limiting rings

An appropriate model for punch-through (PT) limited breakdown voltage of a planar junction is presented for the first time as a function of the normalized epitaxial layer thickness and the critical depletion width of the cylindrical junction at breakdown in non-PT case. The results are applied to the planar junction structure with a single ring, taking into account three different breakdown modes. The problem of the multiple ring structure is solved using the equivalent ring method, which allows determination of the PT limited breakdown voltage and optimized ring spacings for the structure. Comparisons with two-dimensional device simulations using MEDICI show a good agreement.     

A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

A novel analytical model of the vertical breakdown voltage (V_{B , V} ) on impurity concentration (N_d ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy ε_T in the electron, a new formula of silicon critical electric field E_{S , C} on N_d is derived by solving a 2D Poisson equation, which increases with the increase in N_d especially at higher impurity concentration, and reaches up to 68.8?V/µm with N_d  = 1 × 10¹⁷?cm^?3 and 157.2?V/µm with N_d  = 1 × 10¹⁸?cm^?3 from the conventional about 30?V/µm, respectively. A new physical concept of critical energy ε_B is introduced to explain the mechanism of variable high E_{S , C} with heavy impurity concentration. From the E_{S , C} , the expression of V_{B , V} is obtained, which is improved with the increasing N_d due to the enhanced E_{S , C}. V_{B , V} with a dielectric buried layer thickness (t_I ) of 2?µm increases from 428?V of 1 × 10¹⁷?cm^?3 to 951?V of 1 × 10¹⁸?cm^?3. The dependence of N_d and top silicon layer thickness (t_S ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.     

A novel complementary N+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+-regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (E1) and reduce the electric field of the silicon layer (Es), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a l-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field E1 and reduced field Es by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.     

A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.     

300V以上硅基新型JBS肖特基二极管的制备

为了在保留传统肖特基二极管正向压降低、电流密度大优点的基础上,使其反向击穿电压提高到了300 v以上,我们采用硅材料做为衬底,肖特基结区采用蜂房结构,终端采用两道场限环结构加一道切断环结构,所制备的肖特基二极管在正向电流10A时,正向压降仅为0.79 V;同时在施加300 V反向电压时,反向漏电流在5μA以下.     

一种新的互补N+-电荷岛SOI高压器件

本文提出一种新的互补n＋界面电荷岛结构的SOI高压器件（CNI SOI）及其耐压模型。该结构在SOI器件埋介质层上下界面形成等距的高浓度n＋区。当器件外加高压时,在上下界面的两个n+区间形成互补的空穴和电子电荷岛。引入的界面电荷能有效增强埋介质层电场EI,降低顶层硅电场ES,有效提高器件的击穿电压。本文详细研究CNI SOI工作机理及相关结构参数对BV的影响,在1μm介质层、5μm顶层硅上二维仿真获得731V/μm的EI 和 750V的BV,其中增强的△EI和降低的△ES分别达到641.3 V/μm和23.73V/μm。     

一种新型的用于开关电源的高压启动电路

文章提出了一种给集成开关电源提供初始电压的高压启动电路。一个增强型的VDMOS晶体管被用来提供启动电流和承受高压。VDMOS的栅被一个浮空P岛偏置。启动电路用了一个具有高的源对地击穿电压的NMOS来获得大的偏置电压范围。仿真结果表明高压启动电路能够按照设计正常的启动和重启动。本文提出的结构比起其它方案来更节能,成本更低。     

A novel high voltage start up circuit for an integrated switched mode power supply

A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply(SMPS) is presented.An enhanced mode VDMOS transistor,the gate of which is biased by a floating pisland, is used to provide start up current and sustain high voltage.An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS.Simulation results indicate that the high voltage start up circuit can start and restart as designe...