Ion implanted contacts to a-Si:H thin-film transistors

Fabrication steps to improve ion implanted source-drain contacts to hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) have been determined. After establishing a contact performance baseline using devices made with Al/intrinsic a-Si:H contacts, improvements were made to the metal/a-Si:H contact scheme using unheated and heated implants, single- and double-level phosphorous implants, a buffered HF acid dip just prior to metal deposition, Al and Al-Si-Cu metallization schemes, and a post-metallization anneal.     

Fabrication of submicrometer MOSFET's using gas immersion laser doping (GILD)

The fabrication of MOSFET's with submicrometer gate lengths using Gas Immersion Laser Doping (GILD) to dope the source-drain and gate regions of n-channel devices is described. The GILD step relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, λ = 308 nm), to drive in a dopant species adsorbed on the clean silicon surface. High dopant concentrations (1 × 10¹⁹to 2 × 10²¹cm^-3) and shallow junctions (600-1000 Å) make this process ideally suited for source-drain formation in submicrometer structures. In this work the transistors are fabricated using an otherwise conventional NMOS process. The resultant devices have similar source-drain Rsheetvalues and lower poly Rsheetwhen compared to devices fabricated using a conventional implanted source-drain and diffused polysilicon gate. Short-channel devices (L_{poly} = 0.9µm) exhibit excellent I-V characteristics and little change in Vt.     

XeCl Excimer laser annealing used in the fabrication of poly-Si TFT's

Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm²/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm². This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.     

Ageing of laser crystallized and unhydrogenated polysilicon thin film transistors

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and then laser crystallized using a single shot ECL (SSECL of SOPRA) with very large excimer laser. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine or diborane to fabricate n-type or p-type transistors respectively.These laser crystallized TFT's show poorer reliability properties than solid-phase crystallized TFT's. This poor stability is explained to originate from the high surface roughness produced by the laser crystallization, which is highlighted from Atomic Force Microscopy observations.Moreover to this conclusion, the behaviour of the threshold voltage shift ΔV_T during positive and negative stresses is checked to the light of a stretched exponential law that is, as supposed, a federative law. This law is explained in hydrogenated amorphous silicon TFT's by a dispersive diffusion coefficient of hydrogen in the disordered material. Taking into account that such relation appears as sufficiently general and, particularly, can describe the behaviour of monocrystalline silicon MOSFET and un-hydrogenated polysilicon TFT's where the hydrogen cannot involved, it can be supposed that it deals with disordered materials and disordered regions in crystalline materials (interface, grain boundary, …..).     

Optimization of silicon-germanium TFT's through the control ofamorphous precursor characteristics

Polycrystalline thin-film transistors (TFT's) are promising for use as high-performance pixel and integrated driver transistors for active matrix liquid crystal displays (AMLCD's). Silicon-germanium is a promising candidate for use as the channel material due to its low thermal budget requirements. The binary nature of the silicon-germanium system complicates the optimization of the channel deposition conditions. To date, little work has been done to perform this optimization, resulting in poor performance for SiGe TFT's. We report on optimization studies done on the low-pressure chemical vapor deposition of SiGe and its effect on TFT performance. We detail the results of a response surface characterization of SiGe deposition, and explain the obtained results in terms of atomistic models of deposition. Optimization strategies to enable the fabrication of high-performance SiGe TFT's are explained, Using these strategies, SiGe TFT's fabricated using solid phase crystallization and a 550°C process are demonstrated, with mobility greater than 40 cm²/V-s. Analysis is also performed on the effect of Ge-catalysis on the maximum optimization range. Results suggest that SiGe may offer enhanced optimization ranges over Si, as a result of this catalysis     

A new technology for fast switching circuits on glass

A low-temperature self-aligned photolithographic process is described to fabricate fast switching digital poly-CdSe thin-film transistors (TFT's) on glass, The use of sintered CdSe-In2Se3mixtures as an evaporation source for the semiconductor resulted in TFT's with attractive static and dynamic characteristics. The measured inverter delay for a 20-µm technology was 75 ns.     

Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature lower than 600°C, are now largely used in many applications, particularly in large area electronics. The reliability of these TFT's under different electrical conditions is then questionable. In this work, Gate bias stress is studied in two types of polysilicon TFT's originated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. As this hydrogenation step is known to improve the TFT's performances but to introduce unstability, the unhydrogenated TFT's are expected to be more stable. The behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TFT's fit with the known model of the n-channel c-Si MOSFET's bias stress. The behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon.     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

The anomalous behavior of hydrogenated/unhydrogenated polysiliconthin-film transistors under electric stress

The characteristics of high-temperature processed thin-film transistors (TFT's) with/without plasma hydrogenation under the stress condition of V_ds=-15 V and V_gs=0 V have been investigated and compared. It is found that, after stress, the subthreshold swing is greatly improved for unhydrogenated TFT's but not for hydrogenated TFT's. Also, the off-state current is deteriorated for unhydrogenated TFT's but, on the contrary, it is improved for hydrogenated TFT's. A model that takes the effect of hydrogen passivation into account is proposed to interpret the anomalous behavior of TFT's under electric stress     

A high-performance polysilicon thin-film transistor using XeClexcimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (⩽600°C) process have field-effect mobilities of 91 cm²/V·s (electrons) and 55 cm²/V·s (holes), and ON/OFF current ratios over 10 ⁷ at V_Ds=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10     

Controlled two-step solid-phase crystallization forhigh-performance polysilicon TFT's

Solid-phase crystallization for polysilicon thin-film transistors (TFT's) is generally limited by a tradeoff between throughput and device performance. Larger grains require lower crystallization temperatures, and hence, longer crystallization times. In this letter, a novel crystallization technique is presented which increases both throughput and device performance, using a two-step process, controlled using an in situ acoustic temperature/crystallinity sensor. A high-temperature rapid thermal annealing (RTA) nucleation step is followed by a low-temperature grain growth step to grow large-grain polysilicon. TFT's have been fabricated with a substantial improvement in throughput and device performance. This promises a high-throughput, high-performance, spatially uniform TFT process     

A strategy for modeling of variations due to grain size inpolycrystalline thin-film transistors

A strategy is presented for modeling of performance variation in polycrystalline thin-film transistors (TFT's) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFT's results in reasonable agreement     

High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

High performance AlGaN/GaN HEMTs with 2.4 μm source-drain spacing

This paper describes the performance of AlGaN/GaN HEMTs with 2.4 μm source-drain spacing. So far these are the smallest source-drain spacing AlGaN/GaN HEMTs which have been implemented with a domestic wafer and domestic process. This paper also compares their performance with that of 4μm source-drain spacing devices.The former exhibit higher drain current, higher gain, and higher efficiency. It is especially significant that the maximum frequency of oscillation noticeably increased.     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Low-temperature polysilicon thin-film transistors fabricated fromlaser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300°C, and produces devices with mobilities up to 450 cm²/Vs, on/off current ratios greater than 10⁷ , without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films     

p-type thin-film transistors with vacuum-deposited crystallized copper-doped germanium films

Copper-doped 10-nm-thick vacuum-deposited Ge films between vitreous aluminosilicate insulator films can be crystallized at 400°C, with hole mobilities of 80 cm²/V.s. They yield stable p-type TFT's with 10⁵on/off ratio which are process-compatible with n-type CdSe TFT's and thus usable for complementary on-board shift registers in active matrix displays.     

Pentacene organic thin-film transistors-molecular ordering andmobility

Pentacene-based organic thin-film transistors (TFT's) with field-effect mobility as large as 0.7 cm²/V·s and on/off current ratio larger than 10⁸ have been fabricated. Pentacene films deposited by evaporation at elevated temperature at low-to-moderate deposition rates have a high degree of molecular ordering with micrometer-sized and larger dendritic grains. Such films yield TFT's with large mobility. Films deposited at low temperature or by flash evaporation have small grains and poor molecular ordering and yield TFT's with low mobility     

The influence of tilted source-drain implants on high-field effectsin submicrometer MOSFETs

Asymmetries in MOSFET high-field effects, such as impact ionization and bipolar snapback, are used to examine the influence of tilted source-drain implants on device reliability. Several process variables, including source-drain implant conditions and anneal time, are varied to determine how they affect these asymmetries. Using two-dimensional process and devices simulations to explain the physical origins of these effects, the lightly doped drain (LDD) structure is shown to offer some immunity to tilt-angle-induced reliability problems. These results are used to suggest guidelines for the design of the LDD structure