基于STM的原子力显微镜的设计及应用

原子力显微镜由于不受物质导电性的限制,已经成为纳米检测和加工的重要手段之一。本文介绍了根据隧道效应检测微悬臂位移的原理自制的原子力显微镜系统,重点讲述了镜体结构及特点。测试结果表明该仪器具有原子量级的分辨率。最后还给出了用该原子力显微镜检测到的几幅试样的三维表面形貌图。     

AFM探针针尖与试件表面接触力计算方法研究

原子力显微镜是利用接近试样表面的探针针尖上的作用力而工作的。针尖与试件表面纳米接触力的变化对表面检测有重要的影响。在分析原子力显微镜工作原理和纳米接触力计算模型基础上,根据Hamaker假设,利用连续介质方法,建立了针尖同试样表面在接近过程中的纳米接触力计算模型;根据Hertzian接触理论,建立了针尖同试样表面在接触压入过程中的接触力的计算模型。通过叠加计算,获得了耦合接近过程和接触压入过程中的接触力计算方法。根据计算模型,利用Matlab编程计算获得了针尖与试样表面纳米接触作用力的变化规律。为提高原子力显微镜的表面检测精度和进行误差分析提供基础。     

原子力显微术

本文首先介绍了原子力显微术的基本理论，其次讨论了原子力显微镜的结构原理，主要报导了一台我们研制的使用光学偏转法检测的原子力显微镜及仪器性能，仪器测试的结果表明我们这台原子力显微镜获得了原子分辨率，最后给出使用这台显微镜的首批实验结果。     

压电微悬臂在原子力显微镜中的应用

微悬臂是原子力显微镜中最重要的部件之一。用压电微悬臂代替常用的Ｓｉ、ＳｉＯ２或Ｓｉ３Ｎ４微悬臂后的原子力显微镜有一些独特的优点。由于压电微悬臂中的压电薄膜具有压电效应，因此它既可致动微悬臂，又可探测微悬臂的位移量，使得原子力显微镜的结构简单、响应速度快、扫描速度加快。文中简要介绍了压电微悬臂的制作过程，分析了压电微悬臂在原子力显微镜中的各种应用及相应的原子力显微镜的工作原理和有关结果，并与普通原子力显微镜进行了比较。     

原子力显微镜及其在激光作用DNA的结构研究中的应用

本文描述了原子力显微镜的基本原理与特点，对原子力显微镜在激光作用ＤＮＡ的结构研究中的成功应用作了介绍。     

原子力显微镜及其在激光作用DNA的结构研究中的应用

本文描述了原子力显微镜的基本原理与特点，对原子力显微镜在激光作用ＤＮＡ的结构研究中的成功应用作了介绍。     

基于大高宽比CD-AFM探针的设计与制备

针对传统原子力显微镜(AFM)探针和关键尺寸原子力显微镜(CD-AFM)探针受限于针尖有效扫描高度较低,无法对深沟槽和大悬垂侧壁结构进行精准扫描成像的问题,提出了一种大高宽比针尖结构的新型CDAFM探针设计与制备方案。开发的新型CD-AFM 探针针尖有效高度为5.1~5.8 μm,高宽比达到14,相较于传统硅基CD-AFM 探针,其有效高度提升了约4倍。利用开发的探针完成了标称深度为2.3 μm、深宽比为4.6的深沟槽样品测试。     

压电微悬臂有原子力显微镜中的应用

微悬臂是原子力显微镜中最重要的部件之一。用压电微悬臂代替常用的Ｓｉ、ＳｉＯ２或Ｓｉ３Ｎ微悬臂后的原子力显微镜有一定独特的优点。由于压电微悬臂中的压电薄膜具有压电效应，因此它既可致动微悬臂，又可探测微悬臂的位移量，使得原子力显微镜的结构简单、响应速度快、扫描速度加快．文中简要介绍了压电微悬臂的制作过程，分析了压电微悬臂在原子力显微镜中的各种应用及相应的原子力显微镜的工作原理和有关结果，并与普通原子力     

原子力显微镜相位成像模式的设计及研究

相位成像模式是近几年发展起来的一种原子力显微镜的检测模式,该模式可以提供丰富的样品表面纳米尺度信息,是形貌像的有利补充。本文给出了一种应用原子力显微镜轻敲模式的相位检测电路,结构简单,工作可靠稳定。通过实验获得了一些样品的相位像。     

原子力显微镜在材料器件工艺中的应用

介绍了原子力显微镜在碲镉汞材料器件工艺测试方面的应用。应用其可以进行磨抛后材料表面的粗糙度测试,接触孔形貌,以及外延后衬底的表面形貌。通过合理的选择扫描参数和探针,可以直观得到样品的表面形貌,接触孔还可以得到孔的尺寸和孔底形貌。尤其在接触孔测试方面,原子力的精度更高,抗干扰能力强且扫描结果更为直观,准确。本文通过对碲镉汞材料器件工艺中不同类型样品测试的介绍,认为原子力显微镜在碲镉汞材料器件工艺测试中发挥了较大的作用。     

Specular spectroscopic scatterometry

Scatterometry is one of the few metrology candidates that has true in situ/in-line potential for deep submicrometer critical dimension (CD) and profile analysis. Most existing scatterometers are designed to measure multiple incident angles at a single wavelength on periodic gratings. We extend this idea by deploying specular spectroscopic scatterometry. Specular spectroscopic scatterometry (SS) is designed to measure the zeroth-order diffraction response at a fixed angle of incidence and multiple wavelengths. This mechanism allows the use of existing thin-film metrology equipment, such as spectroscopic ellipsometers, to accurately extract topographic profile information from one-dimensional (1-D) periodic structures. In this work, we developed the grating tool-kit (gtk), which implements several variants of rigorous coupled-wave analysis (RCWA) to accurately and efficiently simulate diffraction behavior of 1-D gratings. Theoretical simulations using this package show that specular spectroscopic scatterometry can be applied in the current semiconductor manufacturing technology, and can be easily extended to the 0.07-μm generation. We have also applied a library-based profile extraction methodology to resist and poly focus-exposure matrices patterned using 0.25and 0.18-μm lithography and etch technology, respectively, to extract their cross-sectional profiles. Discrepancies between CD-SEM, CD-AFM, and SSS measurements are discussed and explained     

亚65 nm及以下节点的光刻技术

由于193 nm浸入式光刻技术的迅速发展,它被业界广泛认为是65 nm和45 nm节点首选光刻技术.配合双重曝光技术,193 nm浸入式光刻技术还可能扩展到32 nm节点,但是光刻成本会成倍增长,成品率会下降.随着ASML在2006年推出全球第一款EUV曝光设备,人们纷纷看好EUV技术应用到32 nm及以下节点,但是它仍需克服很多技术和经济上的挑战.对于22 nm节点,电子束直写是最可行,成本最低的候选方案,业界将在它与EUV技术之间做出抉择.     

近期光刻用ArF准分子激光技术发展

193 nm ArF准分子激光光刻技术已广泛应用于90 nm以下节点半导体量产。ArF浸没式也已进入45 nm节点量产阶段。双图形光刻（DPL）技术被业界认为是下一代光刻32 nm节点最具竞争力的技术。利用双图形技术达到32 nm及以下节点已经被诸多设备制造商写入自己的技术发展线路。Cymer公司和Gigaphoton公司为双图形光刻开发了高输出功率、高能量稳定性和具有稳定的窄谱线宽度ArF准分子光源。分析了近期发展用于改进准分子激光性能的关键技术：主振-功率再生放大(MOPRA)结构、主振-功率振荡(MOPO)结构,主动光谱带宽稳定技术,先进的气体管理技术。对光刻用准分子激光光源技术发展趋势进行了简要的讨论。     

Metrology technology for the 70-nm node: process control throughamplification and averaging microscopic changes

Below the 70-nm node feature sizes and aspect ratios will require great advances in metrology and defect detection capability. Although the International Technology Roadmap for Semiconductors (ITRS) prediction becomes more aggressive with each revision, isolate gate lengths for the 70-nm node are predicted to be below 40 nm for microprocessors (see 2000 ITRS). 70 nm and below feature sizes and high aspect ratios will be characteristic of on-chip interconnect. Memory devices will achieve line densities that will drive all areas of metrology. The device performance required for increasing clock speed and reducing leakage current has been driving new gate stack materials development which is expected to be ready for manufacture at this node and below. On-chip interconnect will have integrated low κ dielectric, copper metal lines, and copper diffusion barrier layer materials predicted by the roadmap will require interconnect design advancements to meet increased clock speeds even if the present rate of advance in clock speed decreases. In this paper, the key metrology and defect detection trends for wafer manufacture are covered. The best available information on critical dimension, gate stack, and interconnect measurement and data management are described in light of the need to obtain statistically relevant information from microscopic features     

Comparison of Measurement Techniques for Linewidth Metrology on Advanced Photomasks

This paper compares electrical, optical, and atomic force microscope (AFM) measurements of critical dimension (CD) made on a chrome on quartz photomask. Test structures suitable for direct, on-mask electrical probing have been measured using the above three techniques. These include cross-bridge linewidth structures and pairs of Kelvin bridge resistors designed to investigate dimensional mismatch. Overall, the results show very good agreement between the electrical measurements and those made with a calibrated CD-AFM system, while the optical metrology system overestimates the measured width. The uncertainty in each of the measurements has been considered, and for the first time an attempt has been made to describe the levels and sources of uncertainty in the electrical measurement of CD on advanced binary photomasks.      

CMP后的晶圆的测量和评估方法研究

综述了CMP后的晶圆测量方法,比较指出：光学干涉法适宜于测量较厚的薄膜,而椭圆偏振法精度较高,但成本高昂,适宜于测量薄的薄膜。CMP后需要检测晶圆的表面状况,列举了常用的扫描电子显微镜、原子力显微镜和光散射探测仪。扫描电子显微镜常用于特征线宽的测量,其精度可达4nm;原子力显微镜是根据范德华力的原理制造,其探测精度高达0．1nm：但二者最大的缺陷就是操作复杂,成像十分费时。散射探测仪根据光的散射理论制造。可以快捷地全表面成二维图像,是值得推荐的一种测量手段。最后,指出今后的测量技术对半导体工艺的影响。     

纳米CMOS集成电路设计技术和发展趋势

论述了日美等国纳米CMOS集成电路半导体制造工艺的现状和发展趋势,分析说明国外半导体制造技术的战略和发展状况;结合90 nm CMOS工艺设计的超大规模SOC芯片的实践,对纳米CMOS集成电路设计技术进行分析;阐述SOC设计面临的技术难题,并对今后的发展趋势进行了预测。     

基于表面等离子体的微纳光刻技术

首先介绍了光刻技术的发展及其面临的挑战。随着纳米加工技术的发展,纳米结构器件必将成为未来集成电路的基础,而纳米光刻技术是纳米结构制作的基础,基于表面等离子体的纳米光刻作为一种新兴技术有望突破45nm节点从而极大提高光刻的分辨力。介绍了表面等离子体的特性,对表面等离子体(SPs)在光刻中的应用作了回顾和分析,指出在现有的利用表面等离子体进行纳米光刻的实验装置中,或采用单层膜的超透镜(Superlens),或采用多层膜的Super-lens,但都面临着如何克服近场光刻这一难题;结合作者现有课题分析了表面等离子体光刻的发展方向,认为结合多层膜的远场纳米光刻方法是表面等离子体光刻的发展方向。     

Failure analysis method by using different wavelengths lasers and its application

We succeeded in an accurate detection for failure locations on a silicon semiconductor device (hereafter called “IC”) by applying the failure analysis method in which two kinds of laser beams having different wavelengths are simultaneously irradiated on a surface of IC. Short wavelength laser beam (λ=1083nm) causes potential changes in an internal circuit of IC due to generating many electron-hole pairs in the semiconductor. On the other hand, long wavelength laser beam (λ=1360 run) causes an easy operation of parasitic bipolar elements due to increasing temperature of IC by irradiation heat. By combining these effects of two laser beams, the accurate detection of latch-up locations on internal circuits of IC (has been recognized to be difficult up to now) has come possible.     

400-mW single-frequency 660-nm semiconductor laser

Using an angled-grating broad-area structure in GaInP-AlInP material system, we obtain single spatial and longitudinal-mode operation at 660 nm. The grating stabilizes the mode to deliver over 400-mW continuous-wave at room temperature from a 60-μm-wide stripe. This is about ten times higher than conventional distributed-feedback power output levels, and is the highest single-frequency power from a monolithic semiconductor device in this wavelength range. These devices should be useful for single-mode-fiber coupling and in applications where high-wavelength stability is required, such as spectroscopy, interferometry, or metrology