Turbo码中交织器的性能及应用

本文主要介绍了与交织有关的基础理论知识,对交织器的性能参数及交织器的分类进行定义与分析,并给出一系列的数学描述.     

Turbo码中常用的交织技术

本文简要介绍了信道编码的关键技术-交织技术并给出了几种常用的交织器原理与结构。在此基础上着重介绍了适用于Turbo码的几种特殊的交织器。     

短Turbo码的交织器设计

介绍了一种短Turbo码交织器的设计方法 ,给出了一个短交织器的设计例子 ,其仿真结果表明 ,这种交织器对于短Turbo码很有效。在Turbo码帧长度处于 10 0到 10 0 0时 ,与Turbo码使用块交织和伪随机交织相比 ,误码性能有了大幅度的提高。     

Turbo码中交织器的设计及性能分析

在Turbo码理论中,交织器的选择具有重要的地位。分析了Turbo码的编译码方案,然后讨论了交织器在Turbo码设计方面的重要作用,给出了几种交织器的实现方法,并模拟分析了其性能。     

短帧Turbo码交织器的设计

本文给出一种分组交织器与最佳周期交织器相结合对数据进行交织的方案，可应用在短帧Turbo码交织器的设计中。通过对这种交织器的性能进行计算机模拟，本文得出在短帧Turbo码中该交织器的性能优于伪随机交织器和一般的分组交织器的性能。     

Turbo码中常用的交织技术

本文简要介绍了信道编码的关键技术 -交织技术并给出了几种常用的交织器原理与结构。在此基础上着重介绍了适用于Turbo码的几种特殊的交织器。     

Turbo码交织器的VHDL设计

介绍了Turbo码和交织技术，以及交织技术在Turbo码中的重要作用。并提出了一种交织器电路的设计思路，在这种设计下，各种不同类型的交织器具有相同的电路复杂度。根据此设计思路，用VHDL语言的编程设计了交织器的电路，并给出了仿真结果。     

Turbo码中交织器的综合性能分析与设计

在Turbo码理论中,交织器占有重要地位。论文分析了Turbo码的编译码方案,阐明了交织器在Turbo码设计中的重要作用,提出了几种交织器的设计实现方法,并在仿真的基础上对其性能进行了分析。     

基于三维矩阵的Turbo码交织器设计

该文从理论上分析了Turbo码的性能特点,探讨了交织器在Tlurbo码中所起的作用,并分析指出交织器设计的主要参考因素。通过对常用交织算法的分析和比较,提出了一种基于三维(3-D)矩阵的低复杂度交织算法,实验结果验证了该算法具有较好的性能。     

基于Turbo码的交织器设计与实现

在对几种交织器原理进行分析的基础上，通过对其在Turbo码编解码中的应用。结合具体信道进行了性能仿真，最后比较了它的性能。提出了一种优化的设计方案。采用FPGA技术实现并验证了设计的正确性。     

基于结构图设计LDPC码及其性能仿真

提出了使用结构图设计列重为3的正则LDPC校验矩阵。所设计出的校验矩阵具有较大的围长,并且可以改变码长和码率。这些码可以很好的使用在通信和数据存储领域。最后对这些设计出的LDPC码进行了计算机仿真,仿真的数据结果表明:设计出的码在加性白高斯噪声信道下比随机产生的LDPC码有着更为优良的性能。     

A primer on turbo code concepts

The goal of this article is to describe the main ideas behind the new class of codes called turbo codes, whose performance in terms of bit error probability has been shown to be very close to the Shannon limit. In this article, the mathematical measures of a posteriori probability and likelihood are reviewed, and the benefits of turbo codes are explained in this context. Since the algorithms needed to implement the decoders have been well documented by others, they are only referenced here, not described in detail. A numerical example, using a simple concatenated coding scheme, provides a vehicle for illustrating how error performance can be improved when soft outputs from the decoders are used in an iterative decoding process     

New results on serial concatenated and accumulated-convolutional turbo code performance

Previous methods for analyzing serial concatenated turbo codes employing union error bounds are extended to determine the complete output weight enumeration function of the code; this provides the opportunity to employ a more refined bound due to Polytrev, with considerably improved results limited, however, to block lengths of about 256 bits by computational constraints. The method is then applied to a new class of “accumulated-convolutional” codes, which is a simple special subclass of serial concatenated codes inspired by the “repeat-accumulate” codes of Divsalar et al. Performance appears to be superior to that of conventional codes and results are obtained for much longer block lengths, with impressive results in regions approaching channel capacity.     

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2ⁿ-input network can be configured to support any 2ⁱ-input $(0\le i\le n)$ network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130 nm CMOS technology, the design achieves 384.3 Mbps peak throughput at clock rate of 290 MHz with 5.5 iterations. Consuming 4.02 mm² core area and 716 mW power, the decoder has a 1.81 bits/cycle/iteration/mm² architecture efficiency and a 0.34 nJ/bit/iteration energy efficiency, which is competitive with other recent works.     

Improving turbo code error performance by multifold coding

This article presents a simple turbo coding technique to improve the error performance of a convolutional rate-1/3 turbo code by shaping its weight spectrum closer to the binomial weight distribution of a random code. This technique can be applied to both symmetric and asymmetric rate 1/3 turbo codes to achieve additional coding gain     

A turbo code interleaver design criterion based on the performanceof iterative decoding

The performance of a turbo code is dependent on two code properties: its distance spectrum and its suitability to be iteratively decoded. Both these properties are influenced by the choice of interleaver used in the turbo encoder. This paper presents an interleaver design criterion that focuses on the performance of iterative decoding, based on the correlation properties of the extrinsic inputs. Interleavers designed with the proposed criterion achieve very competitive performances, both in terms of convergence rates and error correcting capabilities     

Design and performance of a product code turbo encoding-decoding prototype

This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to 10^?9 and uses programmable gate arrays (Fpga Xilinx circuits). The elementary extendedBch code and the data block size can be modified to fit specifications of different applications.     

On the performance of concatenated convolutional code and Alamouti space-time code with noisy channel estimates and finite-depth interleaving

In this paper, performance of the Alamouti space- time code (STC) [1] and performance of the concatenation between the convolutional code and the Alamouti STC are derived. In order to describe realistic performance issues, we assume that the channel estimates are calculated from linear filters using noisy pilot symbols. We also assume non-quasi- static channels, spatially correlated transmit antennas and finite- depth interleaving. Two types of receivers are investigated for the Alamouti STC, namely, the linear-combining space-time decoder (LC-STD) and the maximum-likelihood space-time decoder (ML- STD). Two types of receivers are investigated for the concatenated system, namely, the LC-STD with the ML convolutional decoder and the joint Alamouti and convolutional ML decoder. The results have shown that the LC-STD is more sensitive to the Doppler spread than the ML-STD. However, since the ML- STD is very sensitive to the channel estimation error, the gains provided by the decoder in fast fading channels will be offset unless an optimized channel estimator is employed. Performance comparisons between the Alamouti systems and the SISO systems indicate that, when the system environment is not ideal, the SISO systems may outperform the Alamouti systems. Lastly, analytical results are compared with simulation results to illustrate the accuracy of the analysis.     

Mapping interleaving laws to parallel turbo and LDPC decoder architectures

For high-data-rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process from/into the memory. This consideration applies to the two main classes of turbo-like codes, i.e., turbo codes and low-density parity-check (LDPC) codes. Contrary to the literature belief, we prove in this paper that there is no need for an ad hoc code design to meet the parallelism requirement, because, for any code and any choice of the scheduling of the reading/writing operations, there is a suitable mapping of the variables in the memory that grants a collision-free access. The proof is constructive, i.e., it gives an algorithm that obtains the desired collision-free mapping. The algorithm is applied to two simple examples, one for turbo codes and one for LDPC codes, to illustrate how the algorithm works.