Modeling spiral inductors in SOS processes

Existing models for simulating spiral inductors fabricated in silicon processes are outgrowths of the PI structure originally employed by Nguyen and Meyer (1990). This structure and its subsequent elaborations work well for inductors in which the dominant loss mechanism is the underlying substrate. For newer processes with very high resistivity or insulating substrates such as Silicon-on-sapphire however, the model breaks down since inductor quality factor Q is then determined predominantly by series trace resistance. Models suitable for use in such processes are proposed and compared with measured data. The new models contain only four to six elements and, unlike the classic PI model, provide a broadband match to measured impedance behavior in both differentially driven and single-ended circuit applications.     

Synthesis of planar inductors in low temperature co-fired ceramic technology

A simple bisection algorithm for the synthesis of planar inductors using a fast electromagnetic analysis algorithm is presented in this work. Both bisection and electromagnetic analysis algorithms are based on a set of heuristic and physical rules obtained from the study of the electromagnetic behavior of these planar devices. With this procedure, the benefits are two fold: (i) the number of iterations is kept moderately low in the synthesis loop, and (ii) the analysis at each iteration step is speed up without compromising accuracy. The algorithm is applied to the development of an inductor library for a low temperature co-fired ceramic process technology.     

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

In this letter, we analyze the effects of temperature (from -50/spl deg/C to 200/spl deg/C) and substrate impedance on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF/sub min/) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum Q-factor (Q/sub max/), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency (f/sub SR/) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and Q-factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance (R/sub s/), the parallel substrate resistances (R/sub sub1/ and R/sub sub2/), and the resistance R/sub s1/ of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.     

Low temperature brazing of chip inductors by abnormal glow discharge plasma

A novel method, by which Cu was deposited on ferrite ceramics with arc-added glow discharge as a precursory procedure and then brazing the ferrite ceramics with vacuum glow discharge, was investigated. This new method can effectively suppress interfacial diffusion and brazing joint oxidation as well as maintain good adhesion in the joint due to low deposition and brazing temperature, the vacuum atmosphere effect, and the cathode sputter-cleaning action of the abnormal glow discharge plasma. The influence of the brazing process parameters on electrical and magnetic properties of the chip inductors is discussed. The optimal deposition and brazing process parameters are presented. Scanning electron microscope line scanning confirms the brazing electrode joints and detected the interfacial diffusion between the joints and the ferrite ceramics.     

Accuracy evaluation of on-wafer load-pull measurements

This paper investigates the residual calibration uncertainty effects in on-wafer load-pull measurements. After the systematic error correction (based on a traditional error-box model) has been applied, the residual uncertainty on absolute-power-level measurements can dramatically affect the accuracy of typical nonlinear parameters such as gain and power-added efficiency under different load conditions. The main residual uncertainty contributions are highlighted both by a theoretical analysis and experiments. Finally, one of the possible causes for intermodulation-distortion measurement errors is shown     

Self-capacitance of inductors

A new method for predicting the stray capacitance of inductors is presented. The method is based on an analytical approach and the physical structure of inductors. The inductor winding is partitioned into basic cells-many of which are identical. An expression for the equivalent capacitance of the basic cell is derived. Using this expression, the stray capacitance is found for both single- and multiple-layer coils, including the presence of the core. The method was tested with experimental measurements. The accuracy of the results is good. The derived expressions are useful for designing inductors and can be used for simulation purposes     

Design of wireless on-wafer submicron characterization system

A wireless technique for the testing of very large scale ICs and wafers is presented. This test technique uses standard CMOS to achieve wireless parametric testing. This technique has virtually no area overhead, minimal power requirements, and no process or design changes are required. Most compelling is that wafer contact is not required, thereby enabling the in-line process control/monitoring of the manufacture of VLSI wafers or chips. Simulations of representative VLSI antenna designs are presented along with experimental results from the implementation of the antenna coupling and communications link. Also presented are specific circuit simulations showing the characteristics of operation under a range of conditions. The technique is demonstrated experimentally in discrete form with operation at voltages as low as 1 V with submilliwatt power levels. This technique can be implemented with a requirement of 1/10 000th the area of a Pentium-class VLSI circuit, allowing contactless testing of wafers before packaging     

Threshold temperature dependence of lateral-cavity quantum-dotlasers

The threshold temperature dependence for quantum-dot (QD) lasers with different degrees of inhomogeneous broadening are compared. By reducing the inhomogeneous linewidth, the “negative” temperature dependence due to thermal coupling of the QD ensemble can be nearly eliminated, Stable ground state lasing is obtained with a single-layer QD density of -5×10¹⁰ cm^-2 for a long cavity laser, while lower gain QDs and shorter cavity lengths lase on well-resolved higher energy levels     

Design of microfabricated inductors

Possible configurations for microfabricated inductors are considered. Inductance can be set by adjusting permeability through control of anisotropy of a permalloy core or via a patterned quasi-distributed gap. A design methodology based on a simple model is proposed. A more accurate model and a numerical optimization are also developed. Design examples for 5- and 10-MHz buck converters and 2.5-MHz resonant converter applications are presented     

The optimization of on-wafer shield-based test fixture layout

The effect of layout design on shield-based test fixture parasitic components is studied in this paper. As a result, guidelines for shield-based test fixture layout design are given. The novel test fixture layout details studied in this paper are a slotted ground plane with different slot orientation, the use of ground-bar extensions in a ground-shielded test fixture, and the upgrade of a ground-shielded test fixture to a fully shielded structure with a common ground. It was found that a slotted ground plane does not increase the ground lead impedance significantly. Thus, successful ground-shielded test fixture processing can be ensured by obeying process stress release design rules. Furthermore, the additional ground bar extensions had a negligible effect on reducing the ground-shielded test fixture ground lead impedance. However, upgrading the ground-shielded test fixture structure to fully shielded reduced the ground lead impedance. Therefore, fully shielded test fixtures are proposed for use with two-port cascade-based deembedding methods, which commonly are incapable of taking into account ground lead parasitic components.     

Compensation for temperature dependence of operational-amplifier gain

Negative temperature-coefficient compensation capacitors can be used to reduce the temperature dependence of operational-amplifier gain at high frequencies. Experimental results show that the temperature dependence can be reduced by more than an order of magnitude.     

Fully automated on-wafer noise characterization of GaAs MESFETs andHEMTs

A technique is described that permits the rapid determination of all four noise parameters of a MESFET or HEMT at wafer level. The fully automated procedure, which has been implemented in the 2-8 GHz range, uses 16 accurately measured, very repeatable source impedance standards. The standards have been selected for optimum coverage of the input impedance plane to result in stable and rapidly convergent least-squares solutions for the minimum noise figure, optimum source impedance, and noise resistance of practical devices. The resultant system is very stable and produces accurate noise parameters for a wide range of devices     

Equivalent circuit model of on-wafer CMOS interconnects for RFICs

This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.     

The temperature dependence of component failure rate

Data from MIL-HDBK-217B is used to examine the temperature dependence of failure rate of electronic components in actual usage. The dependence is much smaller than expected from the published values of activation energy of component failure mechanisms, or assumed in some commonly used rules-of-thumb.     

On the temperature dependence of NBTI recovery

Poly resistors around the device can be used to perform fast in situ heating on a single device on wafer level. This is a commonly used technique to apply time-saving NBTI stress in the production line [[1], [2] Ting-Kang, Chi-Shiun Wang, Kuan-Cheng Su. Self-heating p-channel metal-oxide-semiconductor field-effect-transistors for reliability monitoring of negative-bias temperature instability. Jpn J Appl Phys 2007;46(12):7639–42]. We demonstrate how such a structure can not only be used as a heating element but also as a fast tool for switching the temperature. The cool down process as well as the heating procedure are rigorously analyzed and found to be very fast (<1 s) and independent of the difference between actual and target temperature. Thus, we are able perform NBTI at a certain stress temperature, which generates a certain degradation level, while the recovery itself can be studied at arbitrary temperatures. By using this technique, our understanding of the recovery physics can be probed in an unprecedented manner. In order to guarantee that our measurements probe the ‘classic’ NBTI mechanisms, unpolluted by tunneling currents in thin oxides and the strongly process dependent impact of nitridation, we use PMOS transistors with 30 nm SiO₂ gate oxides.     

Correlation between the temperature dependence of the band gap and the temperature dependence of the enthalpy of semiconductor crystals

The first-principles pseudopotential method of density-functional theory is used to study electron-phonon interactions in silicon. The temperature shift of the indirect band gap, the phonon spectrum, and the enthalpy are calculated consistently within the density-functional theory. The relationship between the temperature dependence of the energy gap ΔE _g(T) and the temperature dependence of the enthalpy ΔH(T) is ΔH(T)=K|ΔE _g(T)|. The physical origin of this correlation is discussed. Fiz. Tekh. Poluprovodn. 32, 1025–1028 (September 1998)     

Temperature-dependent noise characterization and modeling of on-wafer microwave transistors

Thermal investigation is of basic importance to assess key aspects of the performance and the reliability of microwave devices and circuits operating in a critical environment. To this aim, we have designed and realized an efficient thermoelectric chuck for on-wafer probe stations featuring rapid and accurate temperature control over the 220–320 K range. The system has been exploited in the measurement of I–V characteristics, scattering parameters and noise figure of GaAs-based heterojunction devices up to 40 GHz.The results of the temperature-dependent characterization have been subsequently employed in the extraction of noisy electrical models useful for computer-aided design of low-noise microwave circuits. We here describe the details of this low-cost high-performance measurement system and its applications in investigating the temperature dependence of semiconductor device performances.     

On the temperature and voltage dependence of short-term negative bias temperature stress

Initial NBTI degradation is often explained by elastic hole trapping which also considerably distorts long-term measurements. In order to clarify this issue, short-term NBT stress measurements are performed using different temperatures, stress voltages, and oxide thicknesses. The data shows a clear temperature activation and a super-linear voltage dependence, thereby effectively ruling out elastic hole tunneling. Rather, our data supports an explanation based on a thermally activated hole capture mechanism.     

Investigation of current-gain temperature dependence in silicon transistors

This paper presents the results of an investigation of the factors influencing transistor current-gain temperature dependence. Phase one of the investigation demonstrated experimentally that current-gain temperature dependence is an inverse log function of the average active base resistivity. Devices were found to be less temperature sensitive with lighter base doping levels. Phase two of the investigation experimentally demonstrated current-gain temperature dependence to be an inverse exponential function of the emitter doping level. This large temperature dependence is shown to be a possible consequence of an emitter band-gap decrease, presumably caused by the large number of dislocations and lattice deformations at high doping levels. Using the predicted techniques, several runs of epitaxial planar devices were fabricated which had practically no current-gain temperature dependence, and suffered no noticeable loss in other parameters. Current-gain temperature dependence is also thought to be one of the contributors to hot-spot formation and secondary breakdown. To determine if secondary-breakdown capability had been increased, these temperature-insensitive devices were tested to forward secondary breakdown and compared to standard products of the same geometry. The temperature-independent devices were able to withstand a 40-percent increase in operating power before the onset of secondary breakdown. This increase in capability is thought to be the result of less tendency toward hot-spot formation due to decreased thermal regenerative action.     

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.