5G网络中NSA控制面和用户面时延性能分析

不同于2G/3G/4G的独立组网，5G的网络架构分为两种：非独立（NSA）组网和独立（SA）组网。NSA作为非独立架构，能实现5G的快速部署。低时延是5G非常重要的特点，其实现需要一系列技术的有机结合。针对2.6 GHz NR帧结构，结合理论分析和实际案例数据，研究了NSA架构下控制面时延和用户面时延的现状和问题：当前，商用芯片级别的终端控制面时延约为359～510 ms；，开启预调度功能时，NSA好点空口双向用户面时延为11～14 ms，关闭预调度后，用户面时延增加至15～17 ms。为了进一步优化控制面时延性能，可采用设置NSA的锚点与NR子帧同步、将B1的timetotrigger设置得略小等方案；而采取SR周期自适应方式则可以降低用户面时延。并给出了时延优化方案，给NSA网络部署提供了相应的思路和建议。     

LTE网络CSFB建立时延分析及解决方案探讨

简要介绍了LTE系统中语音业务的接入时延的定义,从构成接入时延的各个阶段入手,结合无线接入网优化工作实际的实际情况,详细分析和讨论了影响接入时延的无线侧相关流程,并在此基础之上提出了接入时延优化的具体建议。     

5G SA用户语音业务EPS FALLBACK时延优化方法的研究

EPS FALLBACK(Evolved Packet System FallBack)是5G SA用户的语音业务解决方案之一。5G SA用户在进行语音通话需求时,需从5G网络侧发起EPS FALLBACK请求,通过重定向或切换的方式回落LTE网络,回落后读取4G侧系统消息建立Vo LTE通话,回落时长直接影响用户感知。主要介绍EPS FALLBACK时延相关问题定位思路和处理方法,阐述处理EPS FALLBACK时延问题的规定动作,用于EPS FALLBACK时延优化。     

URLLC低时延的技术研究及业务应用

分析了URLLC技术指标要求和工业互联网应用的要求,介绍了4G用户面时延情况和减少4G时延的技术演进,研究和分析了5G实现URLLC低时延的灵活的帧结构、动态HARQ、MEC,mini slot、自包含帧、免授权调度等技术,实现了URLLC低时延在工业控制和远程手术的业务应用。     

朴素贝叶斯算法在异常感知话单分析中的应用

针对LTE(长期演进)网络质量优化中移动用户业务面感知的定界评估方法,基于LTE用户面XDR(外部数据表示)的速率和时延,引入朴素贝叶斯算法,对网络中各类业务的异常感知XDR进行分析,通过训练集数据得到类别的先验概率和特征项的类条件概率,并应用于后续异常感知业务的自动归属原因分析,以实现快速科学合理的LTE网络异常感知问题的自动定位以及高效准确的原因判断。     

石家庄LTE网络CSFB时延优化研究

LTE建网初期,语音业务目前使用CSFB方式,存在的主要问题为时延较长。2014年,石家庄LTE网络CSFB时延为11.08秒,通过详细分析CSFB信令流程,找出非重要信令开关、TCH立即指配、UE不活动定时器、被叫选择性鉴权等四类可优化参数,分别进行对比验证,时延缩短效果明显,并通过总结优化成果,综合调整网络参数。通过优化调整,在2015年,石家庄CSFB时延已缩短至10秒以内,优化效果显著,有效提升网络运行质量与客户感知。     

VoLTE关键技术及网络优化研究

VoLTE是基于LTE网络提供的全IP音视频解决方法,也是LTE语音最终解决方式,具有良好的发展前景。文章介绍了VoLTE关键技术,从VoLTE呼叫建立时延、eSRVCC切换等方面研究分析VoLTE网络的优化方法,指导VoLTE网络建设和优化。     

LTE与EV-DO互操作性能研究

分析了LTE与EV-DO数据业务互操作方案,非优化切换方案、流程和相关参数,并对非优化切换时延、切换成功率进行实测分析,与脱网重选时延进行对比,提出LTE数据业务互操作方案实施策略与建议,提升用户业务体验.     

DRX对TD-LTE网络端到端时延的影响

针对LTE系统的DRX(非连续接收)机制进行介绍,系统分析DRX机制引入后对TD-LTE网络端到端时延性能的影响,并基于DRX机制打开和关闭前提对TD-LTE网络Ping包端到端时延进行对比测试分析。测试结果表明,DRX机制引入后,不合理的参数设置以及不同的UE(用户终端)处理能力将对网络时延性能产生影响。     

PTN L2/L3设备中LTE业务归属化的研究

文章主要针对地域大跨度大的PTN网络,在PTN LTE核心层中L2/L3设备存在VE接口承载LTE业务混乱,无区域划分现象,导致与不同用户会话虽在同一区域但是X2业务时延不同的研究。该研究能做到统一区域化归属,降低网络时延,保障用户感知。同时为后期核心设备下沉同PTN LTE核心层的对接提供建设思路。     

Low-latency networking:architecture,key scenarios and research prospect

With the advent of delay-sensitive applications and ultra-low latency scenarios,research on low-latency networking is attracting attention from academia,industry,and standards organizations.Understanding the causes of latency and designing corresponding techniques to reduce latency enable the development of emerging applications.The sources of latency according to the layered architecture of the network was analyzed,and summarizes the techniques for reducing the latency.After that,three typical low-latency key scenarios and delay optimization techniques for data center network,5G and edge computing was analyzed.Finally,the opportunities and challenges that may be encountered in the development of low latency networks were presented from the perspectives of network architecture innovation,data-driven latency optimization algorithm and the design of new protocols.     

Optical interconnection reverse data vortex network: performance analysis

Multistage interconnection networks are employed in data centres to interchange information between the processors and memory elements. Data Vortex (DV) is a multistage minimum logic network which can be used in data centres. DV satisfies the requirements of the interconnection networks such as scalability and throughput. However, the latency is on higher side, and reduction in latency can lead to higher throughput. In the present paper, we describe the feasibility and performance analysis of DV architecture in reverse direction. The routing and the possible hardware model of the node switch have been discussed. We present the performance analysis of Reverse Data Vortex (RDV) architecture in terms of throughput, latency and latency distribution. A comparative study with DV on throughput, latency and latency distribution is also presented. The simulation result shows that the decrease in latency of RDV is about 50 % that of DV and this leads to an increase in injection rate of RDV to values more than two times that of DV.     

一种基于延迟插入法和云计算系统的快速电路仿真的研究

为提高高速高密度电路的设计效率,本文对快速电路仿真中常用的延迟插入法进行研究,分析并推导出延迟插入法的仿真计算公式。通过和通用电路模拟程序软件HSPICE的仿真结果进行比较,验证了延迟插入法的有效性;通过在云计算系统中对大规模电路进行仿真计算,验证了延迟插入法的高效性。本文的研究数据表明延迟插入法和云计算系统的结合可以提供一种可靠,高效的快速电路仿真技术,应用这种技术可以提高电路设计效率。     

URLLC超低时延解决方案和关键技术

介绍了5G URLLC超低时延解决方案架构,提出了URLLC超低时延的边缘计算、最优路径协同、用户面加速、端到端时延监控等关键技术,并分析了5G应用对超低时延的具体要求,最后结合5G各类应用的特点提出了URLLC网络的分阶段部署建议。     

一种基于无线局域网的移动检测优化方案

无线局域网采用移动IP实现移动性管理.移动IP切换存在切换时延大,数据包易丢失的问题.切换时延由移动检测时延和注册时延组成,而移动检测时延在其中占主要部分.文章提出了一种移动检测优化方案,采用了自适应绑定的算法,同时充分考虑了域内小范围高频度切换的情况,使移动节点在无线局域网环境中进行快速有效的切换.     

Latency analysis of the Totem single-ring protocol

The Totem single-ring protocol provides reliable totally ordered multicasting of messages to processes in process groups over a single local-area network (LAN) using a logical token-passing ring. The protocol provides two levels of message delivery: delivery in agreed order and delivery in safe order. This paper presents the probability density functions (PDFs) for the latency to message delivery for the Totem single-ring protocol for these two levels of service in the presence of both message loss and token loss. These PDFs are calculated by repeated convolutions of the PDFs for the various components of the latency. The analysis shows that the mean latency to safe delivery is greater than the mean latency to agreed delivery and that the tail of the latency distribution for safe delivery is longer. It also shows that a deterministic arrival process for message generation exhibits lower mean latencies and shorter tails of the latency distribution than a Poisson arrival process     

软件定义网络中面向时延和负载的多控制器放置策略

在多控制器管理的软件定义网络(SDN)中,时延和负载是控制器放置问题(CPP)要考虑的重要因素。该文以降低控制器之间的传播时延、流请求的传播时延和排队时延、均衡控制器间负载为目标,提出一种控制器放置及动态调整的策略,其中包括用于初始控制器放置的负载均衡算法(BCRA)和遗传算法(GA),用于动态调整控制器负载的在线调整算法(ADOA)。以上算法均考虑网络连通性。仿真结果表明:在初始控制器放置时,在保证流请求的传播时延、排队时延和控制器传播时延较低的情况下,BCRA部署在中小型网络中时,其负载均衡性能与GA相近且优于k-center和k-means算法;GA部署在大型网络中时,与BCRA, k-center和k-means算法相比,使得负载均衡率平均提高了49.7%。在动态情况下,与现有动态调整算法相比,ADOA可以保证较低排队时延和运行时间的同时,仍能使负载均衡参数小于1.54。     

Optimum and heuristic transformation techniques for simultaneousoptimization of latency and throughput

Although throughput alone can be arbitrarily improved for several classes of systems using previously published techniques, none of those approaches are effective when latency constraints, which are increasingly important in embedded DSP systems, are considered. After formally establishing the relationship between latency and throughput in general computation, we explore the effect of pipelining on latency, and establish necessary and sufficient conditions under which pipelining does not alter latency. Many systems are either linear, or have subsystems that are linear. For such cases we have used a state-space based approach that treats various transformations in an integrated fashion, and answers analytically whether it is possible to simultaneously meet any given combination of constraints on latency and throughput, The analytic approach is constructive in nature, and produces a complete implementation when feasibility conditions are fulfilled. We also present a suboptimal but hardware efficient heuristic approach for the special case of initially-relaxed single-input single-output linear time-invariant computations. A novel software platform consisting of a high-level synthesis system coupled to a symbolic algebra system was used to implement the proposed algorithm transformations. Instead of optimizing to improve throughput and latency, our transformations can also be used to increase the implementation efficiency while achieving the same latency and throughput as the original design     

Algebraic survivor memory management design for Viterbi detectors

The problem of survivor memory management of a Viterbi detector is classically solved either by a register-exchange implementation which has minimal latency, but large hardware complexity and power consumption, or by a trace-back scheme with small power consumption, but larger latency. Here an algebraic formulation of the survivor memory management is introduced which provides a framework for the derivation of new algorithmic and architectural solutions. This allows for solutions to be designed with greatly reduced latency and/or complexity, as well as for achieving tradeoff between latency and complexity. VLSI case studies of specific new solutions have shown that at minimal latency more than 50% savings are possible in hardware complexity as well as power consumption