VLSI parallel architecture for Kalman filterAn algorithm specific approach

An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed.     

A low crosstalk microoptic liquid crystal switch

A total internal reflection liquid crystal optical switch has been developed which gives crosstalk levels of -33 dB and switching speeds of 4 ms, with low operating voltage. A novel architecture for larger switch arrays is also proposed and prototype device constructed and tested. The effects of modulation on the optical carrier by the electrical drive signal, and methods of minimizing its effect are reported. Finally, a novel space-saving architecture is proposed and demonstrated for 4×4 switch arrays and its performance reported     

Two-dimensional median filter algorithm for parallel reconfigurablecomputers

A fast and flexible median algorithm is presented which scales well with window size. It is based on the use of image histograming. Two accumulator arrays are used to determine the median value of a discrete sequence of numbers. Speed-up factors of 3 and 4 are achieved over conventional histograming methods (those using single accumulator arrays). Two approaches have been implemented with optimisation in mind. Worst- and best case machine performance boundaries are defined. Timings are given for both types of parallel architecture     

一种可重构阵列结构及其任务调度算法

提出了一种可以利用计算时间覆盖配置时间和数据传输时间的可重构阵列结构,并且针对该可重构阵列结构提出了一种表调度算法进行任务调度.在SOCDesigner平台上进行了软硬件协同仿真,对于IDCT,FFT,4×4矩阵乘法新可重构阵列相比原来的可重构阵列有平均约10%的速度提升.     

On minimizing memory in systolic arrays for the dynamic time warping algorithm

New systolic architectures have been evaluated for the Dynamic Time Warping (DTW) algorithm. This algorithm is a non-linear pattern matching technique used in isolated and continuous speech recognition systems.The proposed systolic decomposition for the DTW algorithm combines simultaneously (1) simple and regular systolic communication schemes and (2) a decomposition strategy which aims at a minimum amount of memory.This approach has led to a systolic architecture which is relatively flexible, compact and easy to test. Several arrays can be built up by keeping the same decomposition of the DTW-algorithm. This allows an easy exchange, depending on the desired application, of execution speed against chip-area.     

1.7 Gbit/s multiplexing-demultiplexing system for a high-bit-rate optical link

A multiplexing-demultiplexing system for a 1.7 Gbit/s link on a single-mode optical fibre has been implemented. The letter first describes the system architecture employed, in order to simplify the technological problems. Details of the electronic circuits used are given next: silicon MSI and cell arrays for the lower-speed stages, GaAs discrete MESFETs and ICs in the high-speed stage.     

一种基于方差融合的双均匀线阵阵列测向算法

本文提出了一种基于双均匀线阵的快速高精度测向算法。针对双均匀线阵不同轴上的接收噪声互不相关的特点,可以得到理论上不含噪声的互相关矩阵。并且由于在两个轴上的阵列流型均具有移不变特性,因此本文所提的快速算法首先利用x轴上最大不重叠的两个子阵列对y轴上最大不重叠的子阵列做互相关,利用y轴上最大不重叠的两个子阵列对x轴上最大不重叠的子阵列做互相关,接着对上述两个相关矩阵采用旋转不变子空间算法,分别计算出目标的角度,再利用方差融合的方法,将两次求得的角度信息进行融合,最后得到较高精度的角度信息,理论分析表明该算法是无偏的,并且在较高信噪比下趋近于克拉莫罗界。最后利用蒙特卡洛仿真验证了本算法的有效性。      

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.     

A Novel VLSI Architecture of SPIHT Using Breadth First Search for Real-Time Applications

A bit-plane parallel architecture for a modified set partitioning in hierarchical trees (SPIHT) without lists algorithm, which uses breadth first search scheme, is proposed. The breadth first search scheme is suitable for very large scale integration (VLSI) implementation based on the analysis of SPIHT algorithm. The architecture has advantages of high parallelism, no intermediate buffer as a single tree is scanned. After field programmable gate arrays (FPGAs) synthesis and simulation, the throughput of the proposed architecture can reach 60 MSample/Sec. As the breadth first search scheme is very similar to that of SPIHT with lists, the quality of reconstructed images is almost the same with that of SPIHT with lists.     

Efficient VLSI for Lempel-Ziv compression in wireless datacommunication networks

We present a parallel algorithm, architecture, and implementation for efficient Lempel-Ziv (LZ)-based data compression. The parallel algorithm exhibits a scalable, parameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design methodologies, two semisystolic array architectures have been developed which are low power and area efficient. The first architecture trades off the compression speed for the area and has a low run-time overhead for multichannel compression. The second architecture achieves a high compression rate (one data symbol per clock) at the expense of the area due to a large clock load and global wiring. Compared to a recent state-of-the-art parallel architecture, our first array structure requires significantly less chip area (≃330 k versus ≃36 k transistors) and more than an order of magnitude less power (≈1.0 W versus ≈70 mW) while still providing the compression speed required for most data communication applications. Hence, data compression can be adopted in portable data communication as well as wireless local area networks. The second architecture has at least three times less area and power while providing the same constant compression rate. To demonstrate the correctness of our design, a prototype module for the first architecture has been implemented using 1.2 μ complementary metal-oxide-semiconductor (CMOS) technology. The compression module contains 32 simple and identical processors, has an average compression rate of 12.5 million bytes/s, and consumes 18.34 mW without the dictionary (≈70 mW with a 4.1k SRAM for the dictionary) while operating at a 100 MHz clock rate (simulated)     

阵列天线在OFDM系统下行链路中的应用

正交频分多址(OFDM:orthogonal frequency division multiplexing)技术由于其在多径环境下克服码间干扰的固有特点,在移动通信中已得到广泛地应用。利用阵列天线上行链路信号到达角估计实时信息,计算OFDM系统下行链路阵列天线权重,将阵列天线应用于下行链路中,最后给出系统误码率性能的计算机仿真结果。     

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise.     

Recurve piezoelectric-strain-amplifying actuator architecture

Various external and internal leverage devices have been developed to amplify strain; however, these devices are commonly inefficient due to transmission losses and can be difficult to pack into constrained application volumes. A Recurve actuator architecture has been designed which amplifies direct material strains and allows for construction of highly compact, high-energy-density actuator arrays. The Recurve architecture enables arrays that can be tailored to produce specific force and displacement output and can be configured in a variety of ways to make efficient use of available design space. This paper describes a Recurve actuator architecture and presents a quasi-static model relating voltage, force, and deflection along with experimental results for fundamental Recurve actuator elements     

The Intelligent RFID Information Security Integrated Antenna Arrays System Based on SOA

Radio frequency identification (RFID) technology system is quickly evolved many applications to manage personnel can be more efficient for automation systems. We combine the RSA encryption and decryption algorithms to raise the safety and the information security systems. The RFID environment has been communicated to exchange data for heterogeneous wireless networks. In this paper, it is implemented the RFID-based campus system solutions to security and privacy of RFID system for wireless mesh network applications. We propose to enhance the security algorithm combined RFID devices for the antenna arrays system. This paper is also presented the integrated framework for the application and integration systems based on service oriented architecture, and given a specific application of the framework combined with campus system.     

A dense overlapped linear subarray architecture for interference suppressing in small‐scale arrays

Compared to omnidirectional antennas, smart antenna arrays are qualified such advantages as lower interference and better spatial reuse. As developed from large‐scale phased array radar, subarray technology is a key approach to reduce the computational complexity, and a quantity of algorithms for subarray partition and low sidelobe has been studied and applied in radar system. With the development of hardware manufacture, portability and mobility are the trend of devices, which limit the array aperture and number of elements, and the performances are constrained by elements number. This paper proposes a dense overlapped subarray architecture for linear array when elements number is small, to improve the array gain and output signal to interference plus noise ratio, and different weighting mode is employed at element and subarray level for adaptive digital beamforming to obtain special performances. The subarray partition is presented for the linear array, which keeps the spacing at subarray level half wavelength to avoid grating lobes and nulls, and the simulation results demonstrate that the subarray architecture induces better output signal to interference plus noise ratio; meanwhile, the computational amount is reduced. Copyright © 2014 John Wiley & Sons, Ltd.     

多用户毫米波MIMO系统中基于信道互易性的混合模数预编码算法

本文针对多用户毫米波多输入多输出(Multiple Input Multiple Output,MIMO)系统,首次提出了分离子阵列MIMO混合模数预编码架构毫米波系统的一种模拟接收方案。将最大化和速率求解混合模数预编码的三元联合优化问题分成模拟和数字两部分求解,进一步提出了基于信道互易性的混合模数预编码算法。该算法通过最大化下行各个用户和上行各个子阵列的接收信干噪比分别求解模拟合并矢量和模拟预编码矢量;优化模拟部分后,设计发射端数字预编码器消除多用户数据流之间的干扰。数值仿真表明所提算法收敛速度快,且可获得接近最优纯数字预编码算法的性能。      

A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule

This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopic capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-muW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-mum CMOS process with 6.2 mW     

On supercomputing with systolic/wavefront array processors

In many scientific and signal processing applications, there are increasing demands for large-volume and/or high-speed computations which call for not only high-speed computing hardware, but also for novel approaches in computer architecture and software techniques in future supercomputers. Tremendous progress has been made on several promising parallel architectures for scientific computations, including a variety of digital filters, fast Fourier transform (FFT) processors, data-flow processors, systolic arrays, and wavefront arrays. This paper describes these computing networks in terms of signal-flow graphs (SFG) or data-flow graphs (DFG), and proposes a methodology of converting SFG computing networks into synchronous systolic arrays or data-driven wavefront arrays. Both one- and two-dimensional arrays are discussed theoretically, as well as with illustrative examples. A wavefront-oriented programming language, which describes the (parallel) data flow in systolic/wavefront-type arrays, is presented. The structural property of parallel recursive algorithms points to the feasibility of a Hierarchical Iterative Flow-Graph Design (HIFD) of VLSI Array Processors. The proposed array processor architectures, we believe, will have significant impact on the development of future supercomputers.     

JPEG2000中小波滤波器的定点分析及其VLSI实现

对JPEG2 0 0 0中推荐的 5 /3整数滤波器和 9/7实数滤波器进行了硬件实现时所需要的有限精度分析 ;确定了小波变换过程中各个参数的最佳数据宽度 ,还确定了整个变换系统的数据通路的数据宽度。基于lifting的小波变换的特点结合嵌入式延拓算法提出了两种小波变换———折叠结构和长流水线结构 ;对两种结构进行了分析比较。最后 ,对折叠结构和相关的其它结构在所需存储单元的数量、存储单元的访问次数、处理能力以及功耗等方面进行了分析比较 ,可以看出文中提出的结构在性能上有明显优点。