An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

A wide-range delay-locked loop (DLL) with infinite phase shift and digital-controlled duty cycle is presented. By changing the polarity of the input clock of the voltage-controlled sawtooth delay, this proposed DLL achieves infinite phase shift by only a single loop. The proposed DLL has been fabricated in a 0.18$ mu$m CMOS process and the core area is $hbox{0.45}times {hbox{0.3 mm}}^{2}$. The measurement results show the proposed DLL operates from 50 to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured rms jitter and peak-to-peak jitter is 1.43 and 11.1 ps, respectively. Its power consumption is 6 mW for a supply of 1.5 V.      

A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-$mu$m CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced tank impedance and even harmonic noise filtering to achieve low phase noise. A third-order 2-bit single-loop $Sigma Delta$ modulator is optimized for the proposed synthesizer in terms of phase noise and power. The synthesizer provides a frequency resolution of 25-kHz with a tuning range from 1.03 GHz to 1.4 GHz . Phase noise of ${-}$70 dBc/Hz inband, ${-}$104 dBc/Hz at 200-kHz offset and ${-}$ 121 dBc/Hz at 1-MHz offset with a reference spur of ${-}$84 dBc are measured at a center frequency of 1.17 GHz and a loop bandwidth of 35 kHz. Power dissipation is 4.92 mW from a 0.8 V supply.      

A Delay-Locked Loop With Statistical Background Calibration

A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18- $mu$m CMOS process. Its active area is 0.078 ${hbox {mm}}^{2}$ . The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz.      

A 1.2-GHz Comparator With Adaptable Offset in 0.35- $mu$m CMOS

We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-$mu$m CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600$times$ and to accurately program a desired offset with maximum observed residual offset of 469 $mu$V and standard deviation of 199 $mu$ V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from ${-}1$ to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.      

A 1.8 V 900 $mu$ W 4.5 GHz VCO and Prescaler in 0.18 $mu$m CMOS Using Charge-Recycling Technique

This letter presents a charge-recycling VCO and divider in 0.18 $mu$m CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 $mu$W of power consumption and ${-}184$ dBc/Hz of FoM at 1.8 V.      

A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation

A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital ${Sigma}{Delta}$ modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the ${Sigma}{Delta}$ modulator can be improved at the same time. The order of the ${Sigma}{Delta}$ modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18- $mu$m CMOS process. The size of the chip area is $hbox{0.44} times hbox{0.48 mm}^{2}$. The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.      

Integrated Multilayered On-Chip Inductors for Compact CMOS RFICs and Their Use in a Miniature Distributed Low-Noise-Amplifier Design for Ultra-Wideband Applications

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-$mu$m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288$,times,$291 $mu$m or 0.08 mm $^{2}$ of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than ${-}$ 12 and ${-}$25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8–10 GHz, while the power consumption is approximately 22 mW.      

A Millimeter-Wave (23–32 GHz) Wideband BiCMOS Low-Noise Amplifier

This paper presents a 23–32 GHz wideband BiCMOS low-noise amplifier (LNA). The LNA utilizes coupled-resonators to provide a wideband load. To our knowledge, the proposed LNA achieves the widest bandwidth with minimum power consumption using 0.18 $mu$m BiCMOS technology in K-band. Analytical expressions for the wideband input matching, gain, noise figure and linearity are presented. The LNA is implemented using 0.18 $mu$m BiCMOS technology and occupies an area of 0.25 mm$^2$ . It achieves a voltage gain of 12 dB, 3-dB bandwidth of 9 GHz, noise figure between 4.5–6.3 dB, linearity higher than ${-}$6.4 dBm with a power consumption of 13 mW from a 1.5 V supply.      

A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the $gm/gds$ ratio of the current sources can be achieved. A power supply rejection of $>,$22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80$~$ pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25–5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7$~$V and a clock frequency of 1.6 GHz.      

A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop

A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 $hbox{mm}^{2}$. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively.      

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 $mu$m digital CMOS process operates from 0.5 to 2.5$~$GHz. At 1.5$~$GHz, the proposed PLL achieves 1.9$~$ ps long-term rms jitter and a worst case supply-noise sensitivity of ${-}$28$~$dB (0.5$~$rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.      

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.      

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13- $muhbox{m}$ standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 $hbox{mm}^{2}$.      

A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

This paper describes a time-to-digital converter (TDC) with $sim $1.2 ps resolution and $sim $327 $mu$s dynamic range suitable for laser range-finding application for example. The resolution of $sim $1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation $sigma $-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 $mu{hbox {m}}$ CMOS process.      

A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique

A 0.18 $mu$ m CMOS quadrature voltage-controlled oscillator with an extremely-low phase noise is presented. The excellent phase noise performance is accomplished by integration of the back-gate quadrature phase coupling and source resistive degeneration techniques into a complementary oscillator topology. The measured phase noise is as low as ${-}133$ dBc/Hz at 1 MHz offset from 3.01 GHz. The output phase imbalance is less than 1$^{circ}$ . The output power is $-1.25{pm} 0.5$ dBm and harmonic suppression is greater than 30.8 dBc. The oscillator core consumes 5.38 mA from a 1.5 V power supply. This QVCO achieves the highest figure-of-merit of ${-}193.5$ dBc/Hz.      

A Differential Clapp-VCO in 0.13 $mu{rm m}$ CMOS Technology

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 $mu{rm m}$ CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank Clapp-VCO using a series-tuned resonator. At the supply voltage of 0.9 V, the output phase noise of the VCO is $-$110.5 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 18.78 GHz, and the figure of merit is $-$188.67 dBc/Hz. The core power consumption is 5.4 mW. Tuning range is about 3.43 GHz, from 18.79 to 22.22 GHz, while the control voltage was tuned from 0 to 1.3 V.      

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.      

A Low Voltage Quadrature VCO Implemented With Series Frequency Doublers

Using the transformer coupling technique, this letter presents a new quadrature voltage-controlled oscillator (QVCO) with bottom series-coupled transistors. The proposed CMOS QVCO has been implemented with the TSMC $0.13~mu{rm m}$ 1P8M CMOS process, and the die area is $1.03 times 0.914~{rm mm}^{2}$. At the supply voltage of 1.0 V, the total power consumption is 3.56 mW. The free-running frequency of the QVCO is tunable from 5.43 GHz to 5.92 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz frequency offset is $-117.98~{rm dBc/Hz}$ at the oscillation frequency of 5.5 GHz and the figure of merit (FOM) of the proposed QVCO is $-187.27~{rm dBc/Hz}$.      

Intraretinal layer segmentation of macular optical coherence tomography images using optimal 3-D graph search

Current techniques for segmenting macular optical coherence tomography (OCT) images have been 2-D in nature. Furthermore, commercially available OCT systems have only focused on segmenting a single layer of the retina, even though each intraretinal layer may be affected differently by disease. We report an automated approach for segmenting (anisotropic) 3-D macular OCT scans into five layers. Each macular OCT dataset consisted of six linear radial scans centered at the fovea. The six surfaces defining the five layers were identified on each 3-D composite image by transforming the segmentation task into that of finding a minimum-cost closed set in a geometric graph constructed from edge/regional information and a priori determined surface smoothness and interaction constraints. The method was applied to the macular OCT scans of 12 patients (24 3-D composite image datasets) with unilateral anterior ischemic optic neuropathy (AION). Using the average of three experts' tracings as a reference standard resulted in an overall mean unsigned border positioning error of 6.1 $pm$ 2.9 $mu$m, a result comparable to the interobserver variability (6.9 $pm$ 3.3 $mu$m). Our quantitative analysis of the automated segmentation results from AION subject data revealed that the inner retinal layer thickness for the affected eye was 24.1 $mu$m (21%) smaller on average than for the unaffected eye $(p≪0.001)$, supporting the need for segmenting the layers separately.