Experimental comparisons in the electrical performance of long and ultrashort gate length GaAs MESFET's

Electrical properties of GaAs single-gate and dual-gate MESFET's with gate lengths of 1.2 µm and 0.2 µm have been compared. By reducing the gate length to 0.2 µm, a very high zero-gate-bias drain current Idssand a large increase in the pinchoff voltage were observed in both single-gate and dual-gate devices, Idssin the shorter gate FET was found to be very close to the full channel current. Only a slight improvement in the maximum intrinsic gmwas noted in the 0.2 µm FET's. The knee voltage for the zero-gate-bias curve was larger in the shorter gate FET. At low current levels, soft pinchoff and soft saturation behaviors were observed in the very short gate FET's. A striking feature of the GaAs MESFET is that its output conductance at large drain voltages does not degrade with shorter gate lengths.     

0.2 Micron length T-shaped gate fabrication using angle evaporation

A new technique has been developed to generate sub-half-micron T-shaped gates in GaAs MESFET's. The technique uses a single-level resist and an angle evaporation process. By using this technique, T-shaped gates with lengths as short as 0.2 µm near the Schottky interface have been fabricated. Measured gate resistance from this structure was 6.1 Ω/mm gate width which is the lowest value ever reported for gates of equal length. GaAs single- and dual-gate MESFET's with 0.3 µm long T-shaped gates have also been fabricated. At 18 GHz, maximum available gain of 9.5 dB in the single-gate FET and maximum stable gain of 19.5 dB in the dual-gate device have been measured.     

Gigabit logic operation with enhancement-mode GaAs MESFET IC's

Enhancement-mode GaAs MESFET IC's have been fabricated using electron-beam lithography. A recessed-gate structure to reduce the gate-to-source resistance and an air-bridge overlay interconnect to reduce stray capacitance were employed. A 30-ps delay time with an associated power dissipation of 1.9 mW is obtained with a 0.6 × 20-µm gate GaAs MESFET, which is the highest speed among the GaAs FET logics. Divide-by-eight counter has exhibited a 3.8-GHz maximum clock frequency with a power dissipation of 1.2 mW/gate.     

GaAs MESFET ring oscillator on Si substrate

GaAs MESFET ring oscillators were fabricated on a Si substrate and successfully operated. Epitaxial techniques to grow a GaAs layer on a Si substrate were investigated. The device-quality GaAs epitaxial layer was obtained by introducing a Ge layer (by ionized cluster-beam deposition) and alternating GaAs/GaAIAs layers (by MOCVD). The typical transconductance of 140 mS/mm was obtained for the FET with a 0.5 µm × 10 µm gate. The minimum delay time was 66.5 ps/ gate at a power consumption of 2.3 mW/gate.     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

Graphical design and iterative analysis of the DC parameters of GaAs FET's

Two-dimensional numerical solutions of Poisson's equation and the carrier continuity equation for the short-gate GaAS field-effect transistor structure have been used to predict device performance. However, a generally accepted simplified approach to FET design has not evolved. In this paper, a simplified design technique and an iterative device analysis procedure are presented for application to GaAs FET's with gate lengths as small as 1 µm. The design technique makes it possible to determine drain saturation current and saturation transconductance for any gate size by simply scaling the appropriate curves for an FET with a 1-µm gate. Curves are also presented that relate the effective transconductance to the intrinsic transconductance for any FET geometry. The iterative analysis procedure makes it possible to determine the doping, ND, and thickness, a, of the epitaxial layer on which the device is fabricated. By simply measuring drain current and transconductance at zero gate bias and the pinchoff voltage, a method is presented which allows the epi parameters to be determined in a self-consistent fashion. This technique provides a way of mapping NDand a over a slice, as opposed to the usual technique of simply measuring pinchoff voltage (only gives ND.a²product variations).     

Improvement in threshold-voltage uniformity in submicrometer GaAs MESFET's using an implanted p layer

A significant improvement in threshold-voltage uniformity for submicrometer gate GaAs MESFET's fabricated by direct Si implan, tation was observed using an optimized p-buried layer on conventional undoped LEC-grown substrates. Using an optimized Be-implantation scheme, we have achieved standard deviations of the threshold voltage as low as 7.6 mV from 13 × 13 FET arrays and only 16.8 mV across a 3-in wafer for FET's with a gate length of 0.6 µm. This is a very promising result for extending the GaAs MESFET IC technology into VLSI circuit complexity.     

GaAs microwave MOSFET's

GaAs microwave metal-oxide-semiconductor field-effect transistors (MOSFET's) with plasma-grown native oxides as gate insulator have been fabricated using a low-temperature magnetically controlled plasma-oxidation technique. A small-signal enhancement device with the gate length of 2.0 µm has demonstrated useful unilateral power gains in the 2-8-GHz frequency range. A maximum frequency of oscillation in the enhancement device is 13 GHz. This is the highest in all enhancement-mode GaAs devices reported up to this time. A medium-power depletion device with the gate length of 1.8 µm has the maximum frequency of oscillation of 22 GHz. This value is 10 percent larger than that of the best analogous metal-semiconductor field-effect transistor (MESFET). The intrinsic current-gain cutoff frequency for the depletion MOSFET is 4.5 GHz which is 22 percent higher than that of the MESFET. The superiority of the depletion MOSFET in the small-signal microwave performance over the MESFET results from the smaller gate parasitic capacitance in the MOSFET as compared to the MESFET. The depletion MOSFET has produced 0.4-W output power at 6.5 GHz as a Class A amplifier. Quite a large frequency dispersion of transconductance is observed in the enhancement MOSFET at a frequency range between 10 and 100 kHz and attributed to interface states. The effect of the interface states does not severely restrict the microwave-frequency capabilities of the enhancement MOSFET as well as the depletion MOSFET since the interface states are unable to follow the input-signal variations at high frequencies.     

A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

A high aspect-ratio 0.1 micron gate technique for low-noise MESFET'S

A new technique, using optical lithography, has been developed to produce very thick submicron gates. This technique has produced Al gates 900Å long and 1.7µm thick, for an aspect-ratio (gate thickness/gate length) of ∼ 19. Using this high aspect-ratio gate structure, GaAs MESFET's have been fabricated with gate lengths as short as 0.1µm and widths as wide as 300µm. Gate resistances of 17Ω/mm and 37Ω/mm of gate width have been measured for half-micron and quarter-micron long Al gates, respectively.     

Principles of operation of short-channel gallium arsenide field-effect transistor determined by Monte Carlo method

The electrical properties of a GaAs FET having a practical doping density and having a quarter-micrometer source-drain distance and a quarter-micrometer gate length have been studied by two-dimensional Monte Carlo particle simulation.I_{ds} = 3.3mA/20µm,g_{m} = 600mS/mm, andf_{T} = 160GHz are predicted. The reasons for the high performances are discussed in terms of the electron dynamics in the device. The current saturation mechanism and the current control mechanism of the FET are made clear.     

High-Frequency Doubler Operation of GaAs Field-Effect Transistors

A comprehensive study of single-gate GaAs FET frequency doublers is presented. Special emphasis is placed on exploring high-frequency limitations, while yielding explanations for previously observed lower frequency phenomena as well. Extensive Iarge-signal simulations demonstrate the underlying relationships between circuit performance characteristics and principal design parameter. Verifying experiments include straight frequency doubler and a self-oscillating doubler, both with output signal frequencies in Ku-band. The self-oscillating doubler appears especially attractive, yielding an overall dc-to-RF efficiency of 10 percent. The type of transistor employed in the numerical and experimental examples possesses a gate length of 0.5 µm and a gate width of 250 µm.     

Monolithic integration of Si MOSFET's and GaAs MESFET's

Integration of Si MOSFET's and GaAs MESFET's on a monolithic GaAs/Si (MGS) substrate has been demonstrated. The GaAs MESFET's have transconductance of 150 mS/mm for a gate length of 1 µm, and the Si MOSFET's have transconductance of 19 mS/mm for a gate length of 5 µm and an oxide thickness of 800 Å. These characteristics are comparable to those for devices fabricated on separate GaAs and Si substrates.     

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.     

A novel camel diode gate GaAs FET

A novel device utilizing the "camel diode" in place of a Schottky barrier gate has been demonstrated in GaAs grown by molecular beam epitaxy (MBE). The devices have a 7.5 µm channel length, 3 µm gate length, and a 280 µm gate width. The layers from which the devices are fabricated consist of a 0.15 µm GaAs layer doped to a level of 1.5 × 10¹⁷cm^-3to form the channel, and a 100 Å p+GaAs and a 400 Å n+ region to form the gate. Because of the long gate length, the electron velocity does not reach saturation, thus a transconductance of 80 mS/mm is obtained. A simple theory describing the device operation has also been developed.     

GaAs LSI-directed MESFET's with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FET's without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.     

Self-aligned submicron gate digital GaAs integrated circuits

Digital normally-off (ENFET) GaAs integrated circuits have been fabricated using a novel self-aligned gate process that has produced high speed ring-oscillators with propagation delays as low as 25 ps and other low power circuits with power dissipation as small as 16 µW (at room temperature). The process is unique in that it permits control of parasitic FET source resistance and gate capacitance and also can achieve submicron gate lengths using conventional optical lithography.     

GaAs MESFET's fabricated on monolithic GaAs/Si substrates

GaAs MESFET's have been fabricated for the first time on monolithic GaAs/Si substrates. The substrates were prepared by growing single-crystal GaAs layers on Si wafers that had been coated with a Ge layer deposited by e-beam evaporation. The MESFET's exhibit good transistor characteristics, with maximum transconductance of 105 mS/mm for a gate length of 2.1 µm.     

Performance prediction for submicron GaAs SDFL logic

We report the results of the computer simulation of GaAs SDFL (Schottky diode FET logic) ring oscillators which takes into account transient effects leading to higher electron velocity in short devices and the fringing capacitances. The results indicate that the delay time decreases from 53.6 ps for 1 µm devices to 28.1 ps for 0.5 µm gate devices, and to 18.6 ps for 0.25 µm devices, with power-delay products of 229, 70, and 27.1 fJ, respectively. When the transient effects are not taken into account, the power-delay product remains nearly the same but the delay time increases with the largest increase to 27 ps for .25 µm devices.     

X-Band Low-Noise GaAs Monolithic Frequency Converter (Short Paper)

An X-band, low-noise GaAs monolithic frequency converter has been developed. Multicircuit functions, such as amplification, filtering, and mixing, were integrated on to a single GaAs frequency converter chip. The frequency converter consists of an X-band three-stage low-noise amplifier, an image rejection filter, an X-band dual-gate FET mixer, and an IF-band buffer amplifier. To minimize circuit size without degrading performances, an RC-coupled buffer amplifier was connected directly after a dual-gate FET mixer IF port, and one-section parallel and series microstrip lines were adopted for the amplifier. One-half-micron (1/2 µm) single-gate FET's and a one-micron (1 µm) dual-gate FET, which have an ion-implanted closely-spaced electrode structure, were used. Either via hole grounds or bonding wire grounds are selectable for the frequency converter. Chip size is 3.4x1.5 mm. The frequency converter provides less than 3-dB noise figure and more than 34-dB conversion gain.