Hot-carrier-induced MOSFET degradation under AC stress

The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.     

Hot-carrier-induced degradation in p-MOSFETs under AC stress

Lifetimes under AC stress are calculated with a quasistatic model using parameters extracted from DC stress data. For inverter-like waveforms, the measurement data show reasonable agreement with the simulation results. For waveforms with turnoff transient occurring in the presence of high drain voltage, more degradation than the model predicts is found if the transient is short (⩽10 ns) and gate voltage is high     

Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Hot-carrier-induced degradation in nitrided oxide MOSFETs

Hot-carrier-induced degradation in commercially prepared silicon-gate MOSFETs incorporating ammonia annealed, nitrided oxides as the gate dielectric is examined and compared with the degradation observed in similar devices incorporating conventional oxides. Nitridation at 1100°C for 2 h is observed to reduce the rate of transconductance degradation and threshold voltage increase by nearly half, compared to the oxide for stressing at both low and high gate bias, and to modify the effects of stressing on the substrate current characteristics. In contrast, nitridation at 1150°C produces both improvements and degradations in device stability depending on the parameter examined and the stress conditions. While ammonia annealing introduces nitrogen, it also appears to incorporate excess hydrogen in the dielectrics that alters charge trapping and interface-state generation so that the performance of the dielectric under electrical stress depends on the concentrations of both species     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

阶梯栅氧结构的NLDMOS热载流子效应研究

本文对一种新型的阶梯栅氧结构的NLDMOS（Step Gate Oxide NLDMOS , SG-NLDMOS）的热载流子效应进行了研究。采用直流电压应力实验、TCAD仿真、电荷泵测试等方法,对退化现象进行了分析,并提出了退化机制。然后研究了漂移区注入剂量对器件热载流子效应的影响,结果表明低的漂移区注入剂量可以更有效地减小器件导通电阻的退化。     

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS(SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment,a TCAD simulation and a charge pumping test.For different stress conditions,degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented.Then the effect of various doses of n-type drain drift(NDD) region implant on R_(on) degradation is investigated.Experimental results show that a lower NDD dosage can redu...     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

Hot-carrier-induced degradation of the back interface inshort-channel silicon-on-insulator MOSFETS

The tolerance of silicon-on-insulator MOSFETs to hot-carrier injection into the buried oxide is investigated. It is shown that stressing of the back channel results in reversible electron trapping and formation of localized defects at the buried interface. This damage is responsible for the transconductance overshoot, large threshold voltage shift, and attenuated kink effect. It is also noticed that even in moderately thin films the back oxide damage does not affect the front-channel operation and, conversely, stressing the front channel does not generate defects at the buried interface. These findings indicate that the hot-carrier degradation of the buried oxide might be chosen as a sensitive criterion for optimizing SIMOX (separation by implantation of oxygen) structures     

Hot-carrier-induced degradation of N2O-oxynitrided gateoxide NMOSFETs

Measurement of long term electrical characteristics of N₂ O-oxynitrided gate oxide NMOSFETs revealed that the role of the nitrogen-rich layer as a blocking barrier for molecular hydrogen diffusion is dominant in the reduced device degradation. A two-step model was proposed, in which the release of hydrogen species and their reaction with the trivalent silicon atoms are the main factors for hot-carrier-induced-degradation. Hot carrier immunity of the NMOSFETs was also found to originate partially from the small increase of both the effective barrier height for electron injection and the interface trap creation energy due to the negatively charged nitrogen-rich layer     

Hot-carrier-induced alterations of MOSFET capacitances: aquantitative monitor for electrical degradation

In this paper, combined gate-to-channel (C_GSD) and gate-to-bulk (C_GB) capacitance measurements are used in order to extract quantitative information about hot-carrier degradation in MOS transistors. An analytical model, explaining the results of accelerated degradation experiments, is presented to establish a simple relationship between C_GSD and C_GB changes and the stress-induced charges Q_ox and Q_it trapped in the oxide or in interface states, respectively. A method, validated by means of two-dimensional (2-D) numerical simulations, is proposed to determine Q_ox and Q_it directly from the measured capacitances, and is applied to experimental data. The new technique considerably improves the capabilities of previous capacitive methods because it can yield a quantitative determination of Q_ox and Q_it     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Thermal gradient in solder joints under electrical-current stressing

The thermal gradient and temperature increase in SnAg3.5 solder joints under electrical-current stressing have been investigated by thermal infrared microscopy. Both positive and negative thermal gradients were observed under different stressing conditions. The magnitude of the thermal gradient increases with the applied current. The measured thermal gradients reached 365°C/cm as powered by 0.59 A, yet no obvious thermal gradient was observed when the joints were powered less than 0.25 A. The temperature increase caused by joule heating was as high as 54.5°C when powered by 0.59 A, yet only 3.7°C when stressed by 0.19 A. The location of heat generation and path of heat dissipation are believed to play crucial roles in the thermal gradient. When the major heat source is the Al trace, the thermal gradient in the solder bumps is positive; but it may become negative because the heat generated in the solder itself is more prominent.     

Mechanism of device degradation in n- and p-channel polysiliconTFTs by electrical stressing

The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation     

Hot-carrier-induced photovoltage in silicon bipolar junction transistors

As bipolar junction transistors (BJTs) are scaled down, the current density increases and base pushout may happen. To prevent base widening, the collector doping concentration is increased; therefore, this increases the electric field in the base-collector junction. In the active operation of BJTs, impact ionization happens and impact-ionization-induced photon emission is created in the base-collector (BC) junction and photon absorption happens in the base-emitter (BE) junction. This makes the carrier injection from the BE junction to the BC junction with avalanche different from that without avalanche. Similarly, the avalanche-induced light emission in the BE junction will induce photocarriers in the BC junction diode. In this paper, we report observation of the photovoltage in the BC junction resulting from hot-carrier electroluminence in the BE junction on a conventional low-power n-p-n bipolar transistor. We found a photovoltage of 0.36 V and a collector current reversal in the inverse active operation.     

Charge trap generation in LPCVD oxides under high field stressing

The degradation of low pressure chemical vapor deposited (LPCVD) oxides, prepared using silane and tetra ethyl ortho silicate (TEOS) as the source, has been investigated under high field stressing. The LPCVD oxides exhibit enhanced conductivity for the Fowler-Nordheim tunneling current, which is modeled as an effective lowering of potential barrier at the injecting electrode. The charge to breakdown (Q_bd) of LPCVD oxides depends on both the deposition chemistry and post deposition annealing condition. The change in interface-state density (ΔD_it), flatband voltage (ΔV_fb), and gate voltage (Δ|V_g|) during constant current stressing are studied to identify the degradation mechanism. We see a very good correlation between Q_bd and Δ|V_g|, indicating that the degradation in LPCVD oxides is dominated by bulk trap generation and subsequent charge trapping. We present a detailed theoretical analysis to substantiate this     

Hot-carrier-induced time dependent dielectric breakdown in high voltage pMOSFETs

We report about the time dependent gate dielectric breakdown failure of high voltage p-channel MOSFETs submitted to hot-carrier stress. We consider the time integral of the instantaneous gate current raised to a constant exponent as a measure of the dielectric film wear out, and we check that this integral computed up to the dielectric failure time is indeed a constant not depending on the drain-source stress bias.