Elimination of Inclusions in (CdZn)Te Substrates by Post-grown Annealing

Post-grown annealing of (211) (CdZn)Te substrates has been used for elimination of Te and Cd inclusions with the objective of improving the yield of inclusion-free substrates for MBE growth of (HgCd)Te. Different annealing temperatures and Cd/Te overpressures were used to find the optimum annealing conditions. Te inclusions were significantly reduced by Cd-rich annealing at temperatures higher than 660°C, together with increasing the infrared transmittance at 10 μm to above 60%. Good crystalline quality was preserved after the annealing. Te-rich annealing at 700°C was found to be the optimum method for elimination of most of the Cd inclusions; infrared transmittance at 10 μm was suppressed by the annealing, however. Final Cd-rich annealing is recommended for infrared transmittance improvement.     

Reduction of Inclusions in (CdZn)Te and CdTe:In Single Crystals by Post-Growth Annealing

(CdZn)Te with the composition of 3% Zn and In-doped CdTe single crystals were annealed at various annealing temperatures and under various Cd or Te pressures with the aim of eliminating Te or Cd inclusions. Te inclusions were reduced by Cd-saturated annealing at temperatures above 660°C. Only small (<1 μm) residual dark spots, located at the original position of as-grown inclusions, were observed after annealing. The size of Cd inclusions was reduced by Te-rich annealing at temperatures higher than 700°C. A specific cooling regime was used to eliminate new small Te precipitates (∼1 μm) concurrently formed on dislocations during Te-rich annealing. Poor infrared transmittance of samples with Cd inclusions was detected after Te-rich annealing; therefore, Cd-saturated re-annealing of annealed samples was used for increasing infrared transmittance to a value above 60%. Alternative models explaining the formation of star-shaped corona-surrounding inclusions are discussed.     

Regular and anomalous-type conversion of p-CdTe during Cd-rich annealing

The kinetics of the p-to-n conversion and effect of the anomalous n-to-p reconversion of p-CdTe during annealing at 400–700°C under Cd-rich overpressure have been investigated. The p-to-n conversion is related to diffusion of Cd interstitials together with gettering of foreign fast diffusing acceptors to the center of the sample. The propagation of the n-type layer during annealing at 500°C was found to be significantly slower then the standard square-root dependence on annealing time. The anomalous n-to-p reconversion of the converted n-type sample was observed after sufficient long time annealing at 600°C.     

A Novel Metal-Rich Anneal for In Vacuo Passivation of High-Aspect-Ratio Mercury Cadmium Telluride Surfaces

A new method for Cd-rich annealing of mercury cadmium telluride (MCT) was developed based on the observation that the deposition of Cd onto MCT by vacuum evaporation became self-limiting whenever the substrate temperature was above 70°C regardless of the Cd evaporation rate. Preliminary results indicated that this new method may be suitable for passivation of high-aspect-ratio MCT surfaces, for passivation at low temperatures, for in vacuo operation, and/or for vacancy annihilation in MCT. Furthermore, the process can be carried out in the conventional open-tube reactors used for molecular beam epitaxy, metalorganic chemical vapor deposition, and physical vapor deposition.     

Effect of isovalent doping with phosphorus on the cluster formation in gallium arsenide grown by molecular-beam epitaxy at a relatively low temperature

Transmitting electron microscopy and X-ray diffractometry are used to study the GaAs layers undoped or doped uniformly with phosphorus (2.3 mol %) and grown at a temperature of 250°C and then annealed isochronously at 400, 500, 600, or 700°C. It is ascertained that doping with phosphorus reduces the amount of excess arsenic captured in the layer in the course of growth and also brings about a retardation of precipitation during subsequent annealing. The concentration of excess arsenic in undoped samples amounted to ～0.2 at %; clusters were observed after annealing at a temperature of 500°C. The concentration of excess arsenic amounted to 0.1 at % in the samples containing phosphorus; in this case, the clusters were observed only after a heat treatment at 600°C. The average size of clusters in doped samples is smaller than that in undoped samples at the same heat-treatment temperatures.     

A comparison of graphite and AlN caps used for annealing ion-implanted SiC

The SiC wafers implanted with Al were capped with AlN, C, or AlN and C and were annealed at temperatures as high as 1700°C to examine their ability to act as annealing caps. As shown previously, the AlN film was effective up to 1600°C, as it protected the SiC surface, did not react with it, and could be removed selectively by a KOH etch. However, it evaporated too rapidly at the higher temperatures. Although the C did not evaporate, it was not a more effective cap because it did not prevent the out-diffusion of Si and crystallized at 1700°C. The crystalline film had to be ion milled off, as it could not be removed in a plasma asher, as the C films annealed at the lower temperatures were. A combined AlN/C cap also was not an effective cap for the 1700°C anneal as the N or Al vapor blew holes in it, and the SiC surface was rougher after the dual cap was removed than it was after annealing at the lower temperatures.     

Inductively coupled plasma etch damage in 4H−SiC investigated by Schottky diode characterization

Ti Schottky diodes have been used to investigate the damage caused by inductively coupled plasma (ICP) etching of silicon carbide. The Schottky diodes were characterized using IV and CV measurements. An oxidation approach was tested in order to anneal the damage, and the diode characterization was used to determine the success of the annealing. The barrier height, leakage current, and ideality factor changed significantly on the sample exposed to the etch. When the etched samples were oxidized the electrical properties were recovered and were similar to the unetched reference sample (with oxidation temperatures ranging from 900°C up to 1250°C). Annealing in nitrogen at 1050°C did not improve the electrical characteristics. A low energy etch showed little influence on the electrical characteristics, but since the etch rate was very low the etched depth may not be sufficient in order to reach a steady state condition for the surface damage.     

Capacitance study of electron traps in low-temperature-grown GaAs

Electron traps in GaAs grown by MBE at temperatures of 200–300°C (LT-GaAs) were studied. Capacitance deep level transient spectroscopy (DLTS) was used to study the Schottky barrier on n-GaAs, whose space-charge region contained a built-in LT-GaAs layer ∼0.1 μm thick. The size of arsenic clusters formed in LT-GaAs on annealing at 580°C depended on the growth temperature. Two new types of electron traps were found in LT-GaAs layers grown at 200°C and containing As clusters 6–8 nm in diameter. The activation energy of thermal electron emission from these traps was 0.47 and 0.59 eV, and their concentration was ∼10¹⁷ cm⁻³, which is comparable with the concentration of As clusters determined by transmission electron microscopy. In LT-GaAs samples that were grown at 300°C and contained no arsenic clusters, the activation energy of traps was 0.61 eV. The interrelation between these electron levels and the system of As clusters and point defects in LT-GaAs is discussed. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 38, No. 4, 2004, pp. 401–406. Original Russian Text Copyright ? 2004 by Brunkov, Gutkin, Moiseenko, Musikhin, Chaldyshev, Cherkashin, Konnikov, Preobrazhenskii, Putyato, Semyagin.     

Investigation of techniques for minimizing resistivity of thin metallic films at submillimeter wavelengths

Experimental investigations of the substrate deposition temperature and annealing temperature influence on aluminum films deposited on diamond substrates were conducted. Tests were performed at direct current and at 101.55 GHz. Minimum resistivity levels, near theoretical predictions, occurred for deposition temperatures in the range of 50–160°C and for peak annealing temperatures of 100–120°C. Both colder and hotter substrate temperatures resulted in larger resistivity levels.     

Variable energy positron beam characterization of defects in as-grown and annealed low temperature grown GaAs

Variable energy positron annihilation measurements on as-grown and annealed GaAs grown by molecular beam epitaxy at temperatures between 230 and 350°C have been performed. Samples were subjected to either isochronal anneals to temperatures in the range 300 to 600°C or rapid thermal anneals to 700, 800, and 900°C. A significant increase in the S-parameter was observed for all samples annealed to temperatures greater than 400°C. The positron annihilation characteristics of the defect produced upon annealing are consistent with divacancies or larger vacancy clusters. The concentration of as-grown and anneal generated defects is found to decrease with increasing growth temperature.     

A novel approach for the complete removal of threading dislocations from ZnSe on GaAs (001)

Here we demonstrate a novel approach to the complete removal of threading dislocations in ZnSe on GaAs (001). This approach, which we call patterned heteroepitaxial processing (PHP), involves post-growth patterning and thermal annealing. Eyitaxial layers of ZnSe on GaAs (001) were grown to thicknesses of 2000–6000 A by photoassisted metalorganic vapor phase epitaxy (MOVPE). Following growth, layers were patterned by photolithography and then annealed at elevated temperatures under flowing hydrogen. Threading dislocation densities were determined using a bromine/methanol etch followed by microscopic evaluation of the resulting etch pit densities. We found that as-grown layers contained more than 107 CM-2 threading dislocations. The complete removal of threading dislocations was accomplished by patterning to 70 gm by 70∼tm square regions followed by thermal annealing for 30 minutes at temperatures greater than 5000C. Neither post-growth annealing alone nor post-growth patterning alone had a significant effect. The effectiveness of this approach dminishes significantly below 500 C so that annealing at 400 C produces no measurable effect. We propose that the underlying mechanism for dislocation removal is the thermally activated glide of dislocations to the sidewalls of patterned regions, as promoted by sidewall image forces.     

Tuning the Properties of CZTS Films by Controlling the Process Parameters in Cost-Effective Non-vacuum Technique

Highly dispersive Cu₂ZnSnS₄ (CZTS) nanoparticles were successfully synthesized by a simple solvothermal route. A low cost, non-vacuum method was used to deposit CZTS nanoparticle ink on glass substrates by a doctor blade process followed by selenization in a tube furnace to form Cu₂ZnSn (S,Se)₄ (CZTSSe) layers. Different selenization conditions and particle concentrations were considered in order to improve the crystallinity and surface morphology; the annealing temperature was varied between 400°C and 550°C and the annealing time was varied between 5 min and 20 min in a selenium-nitrogen atmosphere. The influence of annealing conditions on structural, compositional, optical and electrical properties of CZTSSe thin films was studied. An improvement in the structural and surface morphology was observed with increasing of annealing temperature (up to 500°C). An enhancement in the crystallinity and surface morphology were observed for thin films annealed for 10–15 min. Absorption study revealed that the band gap energy of as-deposited CZTS thin film was approximately 1.43 eV, while for CZTSSe thin films it ranged from 1.15 eV to 1.34 eV at different annealing temperatures, and from 1.33 eV to 1.38 eV for different annealing times.     

High temperature annealing of mnos devices and its effect on si-nitride stress,interface charge density and memory properties

The effects of high temperature annealing in N₂ and H₂ ambients upon the following properties of MNOS devices have been investigated: Si-nitride stress, etch rate, index of refraction, fixed interface charge and fast surface state density, memory window and charge retention at elevated temperatures. The CVD Si-nitride and Si-oxynitride films were deposited at temperatures as low as 610°C with a NH₃/SiH₄ ratio of 1000:1, the heat treatments were performed in the temperature range from 640°C to 1130°C. A similar N₂-annealing behavior was found for film stress and flatband voltage. The film stress increased with increasing annealing time and temperature while the interface charge density changed from high positive values (Q_N/q = 4 × 10¹²cm⁻2) after nitride deposition at 610°C to high negative values (Q_N/q = -4 × 10¹²cm⁻2) after annealing at 930°C, The fast interface state density increased while the charge retention time was drastically reduced. The changes of the properties by N₂ annealing are mainly attributed to decomposition of SiH and NH bonds. Minor effects were obtained by annealing in H₂ and the drastic changes caused by N₂ annealing could be reversed to a great extent by subsequent H₂ annealing. Finally the different effects of deposition and annealing temperature on the propertiesare discussed .     

Thermal stability of heavily tellurium-doped InP grown by metalorganic molecular beam epitaxy

The thermal stability of tellurium in InP has been examined in samples doped with Te up to an electron concentration of 1.4 × 10²⁰ cm⁻³. Annealing was conducted using rapid thermal annealing for a period of one minute at temperatures over the range 650–800°C. Secondary ion mass spectroscopy analysis showed virtually no change in the Te profile before and after annealing, even at the highest annealing temperatures. High resolution x-ray diffraction and Hall measurements revealed a general decrease in the lattice strain and carrier concentration for annealing temperatures above 650°C. No evidence of strain relief was found in the form of cross-hatching or through the formation of a dislocation network as examined by scanning electron microscopy or transmission electron microscopy (TEM). These results are most likely due to the formation of Te clusters, though such clusters could not be seen by crosssectional TEM.     

Structure and Optical Properties of CeO2 Nanoparticles Synthesized by Precipitation

Cerium dioxide (CeO₂) has special electrical and optical properties, and chemical and thermal stability. It has been used in semiconductor devices and as a luminescent material. In this work, CeO₂ nanoparticles were synthesized by the precipitation method and the product annealed at various temperatures. Thermogravimetric analysis (TGA)/differential scanning calorimetry (DSC) results show that the optimum annealing temperature for fabrication of CeO₂ nanoparticles is greater than 500°C. When the calcination temperature is increased from 550°C to 1050°C, Fourier-transform infrared (FTIR) results show that the water and impurities are almost completely removed, after calcination at 750°C. The x-ray diffraction (XRD) results suggest that the synthesized CeO₂ exhibits a cubic fluorite structure. The crystallite size of the CeO₂ increases from 8 nm to 75 nm when the calcination temperature is increased from 550°C to 1050°C. The absorption spectrum in the ultraviolet (UV) region from 372 nm to 395 nm demonstrates their applicability as UV-filter materials, and the shift of the estimated E _g,eff from 3.21 eV to 3.65 eV demonstrates their applicability in photoelectric devices. CeO₂ would be potentially important for applications such as insulator structures, stable capacitor devices, and light-emitting diodes (LEDs).     

The impact of MOCVD growth ambient on carrier transport,defects, and performance of CdTe/CdS heterojunction solar cells

CdTe solar cells were fabricated by depositing CdTe films on CdS/SnO₂/glass substrates in various metalorganic chemical vapor deposition growth ambient with varying Te/Cd mole ratio in the range of 0.02 to 15. The short-circuit current density (J_sc) showed a minimum at a Te/Cd ratio of 0.1 and increased on both sides of this minimum. The open-circuit voltage (V_oc) was found to be the highest for the Te-rich growth ambient (Te/Cd∼6)and was appreciably lower (600 mV as opposed to 720 mV) for the stoichiometric and the Cd-rich growth conditions. This pattern resulted in highest cell efficiency (12%) on Te-rich CdTe films. Auger electron spectroscopy revealed a high degree of atomic interdiffusion at the CdS/CdTe interface when the CdTe films were grown in the Te-rich conditions. It was found that the current transport in the cells grown in the Cd-rich ambient was controlled by the tunneling/interface recombination mechanism, but the depletion region recombination became dominant in the Te-rich cells. These observations suggest that the enhanced interdiffusion reduces interface states due to stress reduction or to the gradual transition from CdS to CdTe. The hypothesis of reduced defect density in the CdTe cells grown in the Te-rich conditions is further supported by the high effective lifetime, measured by time-resolved photoluminescence, and the reduced sensitivity of quantum efficiency to forward/light bias.     

MBE growth and characterization of in situ arsenic doped HgCdTe

We report the results of in situ arsenic doping by molecular beam epitaxy using an elemental arsenic source. Single Hg_1−xCd_xTe layers of x ∼0.3 were grown at a lower growth temperature of 175°C to increase the arsenic incorporation into the layers. Layers grown at 175°C have shown typical etch pit densities of 2E6 with achievable densities as low as 7E4cm⁻². Void defect densities can routinely be achieved at levels below 1000 cm⁻². Double crystal x-ray diffraction rocking curves exhibit typical full width at half-maximum values of 23 arcsec indicating high structural quality. Arsenic incorporation into the HgCdTe layers was confirmed using secondary ion mass spectrometry. Isothermal annealing of HgCdTe:As layers at temperatures of either 436 or 300°C results in activation of the arsenic at concentrations ranging from 2E16 to 2E18 cm⁻³. Theoretical fits to variable temperature Hall measurements indicate that layers are not compensated, with near 100% activation after isothermal anneals at 436 or 300°C. Arsenic activation energies and 77K minority carrier lifetime measurements are consistent with published literature values. SIMS analyses of annealed arsenic doping profiles confirm a low arsenic diffusion coefficient.     

Modeling Si nanoprecipitate formation in SiO2 layers with excess Si atoms

Computer simulations based on the Monte Carlo method are used to analyze processes leading to the formation of luminescence centers in SiO₂ implanted with Si ions. The simulations, which take place in a two-dimensional space, mimic the growth of silicon nanoprecipitates in layers containing several at.% of excess silicon. It is assumed that percolation clusters made up of neighboring Si atoms form first. As the annealing temperature increases, these clusters grow and compactify into nano-sized inclusions of a well-defined phase. It is shown that a dose dependence arises from an abrupt enhancement of the probability of forming direct Si-Si bonds when the concentration of silicon exceeds ∼1 at. %. Under these conditions, percolation chains and clusters form even before annealing begins. The effect of the temperature of subsequent anneals up to 900 °C is modeled via the well-known temperature dependence of Si diffusion in SiO₂. It is assumed that annealing at moderate temperatures increases the mobility of Si atoms, thereby facilitating percolation and development of clusters due to an increase in the interaction radius. Intrinsic diffusion processes that occur at high temperatures transform branching clusters into nanoprecipitates with well-defined phase boundaries. The dose and temperature intervals for the formation of precipitates obtained from these simulations are in agreement with the experimental intervals of dose and temperatures corresponding to the appearance of and changes in luminescence. Fiz. Tekh. Poluprovodn. 33, 389–394 (April 1999)     

The carrier lifetime of heat-treated silicon crystals

Carrier lifetime measurements were performed on crucible-grown, float-zoned, and swirl-free float-zoned silicon single crystals after annealing up to about 1000°C. In dislocation-free, crucible-grown silicon one pronounced maximum of the carrier lifetime can be found after annealing at 450°C . This gettering effect is correlated to the appearence of numerous IR-absorption bands at 80 K. The absorption coefficients of these bands depend on the oxygen concentration of the crystals and on the annealing duration. A differing number of maxima of the carrier lifetime after annealing at various temperatures can be found in dislocation-free, float-zoned silicon. These maxima are correlated to still remaining lattice defects in the crystals such as vacancy clusters of A-and B-type. Models are presented to explain the experimental findings.     

Cl2 chemical dry etching of GaAs under high vacuum conditions—Crystallographic etching and its mechanism

Cl₂ chemical dry etching for GaAs substrates of {111}A, {111}B, {110} and {100} orientations was accomplished under high vacuum conditions. The etch rate for different substrate orientations was {111}B > {110} = {100} > {111}A for temperatures below 450° C, and was nearly equal for temperatures above 450° C. For {111}B, {110} and {100} substrates, the etch rate depends strongly on the substrate temperature above 450° C and below 150° C. Two activation energies for etching (10.0 kcal/mol below 150° C and 16.0 kcal/mol above 450° C) were obtained. Between 150 and 450° C, the etch rate depends weakly on the substrate temperature. However, for {111}A substrate, the etch rate increased monotonically with increasing substrate temperature above 300° C. The activation energy corresponds to that for the other substrates above 450° C. These results are caused by the surface chemical reaction of GaAs/Cl₂. By using these etching properties, a vertical side wall was fabricated without ion bombardment.