Short channel characteristics of Si MOSFET with extremely shallowsource and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 μm while punchthrough is suppressed down to 0.07 μm, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects     

Sub-50-nm physical gate length CMOS technology and beyond usingsteep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with T_ox^inv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions     

Optimization of gate-to-drain separation in submicron gate-lengthmodulation doped FET's for maximum power gain performance

This paper analyzes the effects of the separation between the gate and the drain electrodes on the high-frequency performance limitations of heterostructure MODFET's. Based on the effective gate-length and carrier velocity saturation concepts first the key small-signal equivalent network model parameters of the MODFET are calculated. The concept of open-circuit voltage gain, defined as the transconductance to output conductance ratio (g_m/g_o), has been exploited to determine the output conductance with a knowledge of the static electric field and potential at the edge of the gate on the drain side. By treating the c_oμ_n product as a function of the gate voltage, the drain current-voltage and transconductance characteristics have been effectively modeled for practical devices. By combining the effects of the intrinsic and parasitic equivalent network parameters this paper has determined the dependence of the g_m/g_o ratio, the gate capacitance to the feedback capacitance ratio, the unity current gain frequency (f_r) and the maximum frequency of oscillations (f _max) on the gate-to-drain separation (L_gd). MODFET's based on InAlAs/InGaAs heterostructures lattice-matched to InP substrate with gate-length values of 0.25 μm, 0.15 μm and 0.1 μm are considered for analyses. The optimum values of L_gd calculated are 600 Å, 420 Å, and 340 Å for the corresponding maximum f_max-values of 250, 370, and 480 GHz, respectively     

New experimental findings on hot carrier effects in sub-0.1 μmMOSFET's

The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V_gmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of V_gmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range     

An accurate gate length extraction method for sub-quarter micronMOSFET's

By comparing measured and simulated gate-to-source/drain capacitances, C_gds, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C_gds simulation, the polysilicon gate length, L_poly, can be accurately determined for device lengths down to the 0.1 μm regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L_poly extraction, the source/drain lateral diffusion length, L_diff , and effective channel length, L_eff, can also be determined precisely. The accuracy of L_diff is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile     

0.18-μm fully-depleted silicon-on-insulator MOSFET's

High-performance 0.18-μm gate-length fully depleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance. Nominal device drive currents of 560 μA/μm and 340 μA/μm were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers     

Nonsilicide source/drain pixel for 0.25-μm CMOS image sensor

A nonsilicide source/drain pixel is proposed for high performance 0.25-μm CMOS image sensor. By using organic material spin coat and etch back, silicide is only formed on poly gate which can be used as interconnection, not for source/drain region that solve the optical opaqueness and undesirably large junction leakage of silicide. The performance of MOSFET changes little due to the high sheet resistance of nonsilicide source/drain. With H₂ annealing and double ion implanted source/drain junction, the dark current can be further reduced. The novel pixel (three transistors, 3.3 μm×3.3 μm, fill factor: 28%) shows low dark current (less than 0.5 fA per pixel at 25°C) and high photoresponse     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

Design optimization of high-performance low-temperature 0.18 μmMOSFETs with low-impurity-density channels at supply voltage below 1 V

A 0.18 μm nMOS structure with a vertically nonuniform low-impurity-density channel (LIDC) at 77 K has been studied at supply voltage below 1 volt. An abrupt Gaussian profile is used in the channel. The investigation is based on two-dimensional (2-D) energy transport simulation with appropriate models to account for quantum and low-temperature freeze-out effects. The study focuses on achieving high driving capability and low off-current at low supply voltage and on minimizing short-channel effects. Some guidelines are proposed for improving device performance and suppressing short-channel effects of the LIDC MOS devices. It is shown that at 77 K the optimized nonuniform LIDC 0.18 μm nMOS structure with an abrupt impurity channel profile at supply voltage as low as 0.9 V is able to provide a saturation drain current comparable to that of a room-temperature LIDC 0.1 μm nMOS device at 1.5 V. Furthermore, the 77 K LIDC 0.18 μm nMOS consumes considerably lower dynamic and standby power than the room-temperature 0.1 μm nMOS. These results suggest that the LIDC MOS structure with an abrupt channel profile is very suitable for low-power and high-speed ULSI applications at low temperature     

Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs

We have proposed and simulated a new 10-nm and sub-10 nm n-MOSFET that has a recessed channel and asymmetric source/drain Schottky Contacts (RASC MOSFETs). The recessed channel can effectively suppress short-channel effects, and the asymmetric source/drain contacts in which a higher Schottky barrier at the source contact can yield smaller off-state current while a lower Schottky barrier at the drain can yield larger on-state current. The simulated results show that the device can exhibit an on/off ratio as high as 10⁶ and an on-state current of 393 μA/μm with a supply voltage of 1.0 V. Furthermore, the parameters of RASC MOSFETs are rather insensitive to size variations. These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications     

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds =0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers     

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions     

The characterization of hot carrier damage in p-channel transistors

Damage in surface channel p-MOS transistors arising from hot-carrier stress is examined using a recently proposed lifetime extraction method. It is shown that the p-MOS behavior with respect to hot-carrier stress runs counter to that of n-MOS transistors in many respects and has to be considered separately. Not only are the well-known post-stress gains in drive current obtained for p-MOS transistors, but also the measurement of the I-V characteristics with the stress damage at the source and drain ends shows effects opposite to those of n-MOS devices. This is attributed to coulombic screening by the channel charge. Stressing transistors in inverter-like and pass-transistor-like modes are also discussed, and it is found that p-MOS transistors are much more sensitive to pass-transistor-like damage than n-channel devices, due to increased channel length shortening in the pass transistor mode. It is shown that whereas at long gate lengths (>0.5 μm) the degradation is limited to drain current changes, at shorter channel lengths (<0.5 μm), significant threshold voltage shifts arise     

Sub-40 nm SOI V-groove n-MOSFETs

We present output and transfer characteristics of single-gated, 36 nm, 46 nm and 56 nm channel length SOI MOSFETs with a V-groove design. For the shortest devices we find transconductances as high as 900 μS/μm and drive currents of 490 μA/μm at V_gs - V _th=0.6 V. The V-groove approach combines the advantages of a controlled, extremely abrupt doping profile between the highly doped source/drain and the undoped channel region with an excellent suppression of short-channel effects. In addition, our V-groove design has the potential of synthesizing devices in the 10 nm range     

On the punchthrough phenomenon in submicron MOS transistors

As the channel length of MOS transistors reduces to the submicron dimension, the punchthrough becomes more of a surface-initiated and gate-controlled phenomenon. A surface diffusion current (I_sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (Δφ_so). The DIBL effect increases rapidly with decreasing channel length. In addition, the extracted Δφ_so from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long submicron devices (≈0.62 μm) to the strong-inversion mode for deep submicron devices (≈0.12 μm). In general, I_sdif dominates over the low drain bias range and eventually converts to the bulk space-charge-limited current (I_scl) as the drain bias increases and the source/drain depletion regions connect. The drain bias for this conversion to occur strongly depends on the channel dimension. Only intermediate submicron devices (≈0.37 μm) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components. For long submicron devices, I_sdif essentially dominates, while for deep submicron devices, it converts rapidly to I_scl over the drain bias range investigated. A semi-empirical closed form equation is proposed to describe both I_sdif and I_scl and their merging over the entire range of drain bias     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

Analytical device model for submicrometer MOSFET's

A drain current model applicable to deep submicrometer MOSFETs is proposed. This pseudo-two-dimensional device model includes the velocity overshoot effect by using the extended-drift-diffusion (EDD) model. Calculated current-voltage characteristics agree well with the reported experimental data for deep submicrometer MOSFETs. The model is applicable to small-geometry MOSFETs down to L=0.1 μm, whereas conventional modes without the velocity overshoot are valid to 0.25 μm     

Inverse modeling of two-dimensional MOSFET dopant profile viacapacitance of the source/drain gated diode

This paper proposes and demonstrates a new approach to two-dimensional (2-D) dopant profile extraction for MOSFETs by treating the source/drain-to-substrate junction as a gated diode. The small-signal capacitance of the diode measured as a function of gate and source/drain bias is used as the target to be matched in an inverse modeling process. It is shown that this capacitance allows both the substrate dopant profile in the channel region and the source/drain-to-substrate profile parallel to the surface to be evaluated with a single set of measurement data. Experimental results for n-MOSFET's with drawn channel length =1 μm and 0.265 μm are presented. Comparison of other electrical measurement with simulation data based on the extracted profile is also given     

Comparative analysis of hot electron injection and induced devicedegradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlosimulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 μm SOI n-MOSFETs operating under low voltage conditions, i.e., V_d considerably less than the Si-SiO₂ injection barrier height φ_b. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding φ_b. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 μm SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T_Si experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface     

Threshold voltage sensitivity of 0.1 μm channel lengthfully-depleted SOI NMOSFET's with back-gate bias

We found threshold voltage sensitivity to silicon thickness variation in 0.1 μm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases