Analysis of negative differential resistance in theI-V characteristics of shorted-anode LIGBT's

The physical mechanism responsible for the negative differential resistance (NDR) in the current-voltage characteristics of the shorted anode lateral insulated gate bipolar transistor (SA-LIGBT) is explained through two-dimensional numerical simulation. The NDR regime is an inherent feature of all SA-LIGBTs, and results from the two different conduction mechanisms responsible for current flow in the device. These conduction mechanisms are minority-carrier injection and majority-carrier flow. Since both the anode geometry and the doping profile control the onset and the degree of minority-carrier injection, the effect these parameters have on the NDR is investigated. A simple lumped-element equivalent model of the SA-LIGBT allows qualitative predictions to be made on how changes in the device geometry and doping profiles influence the NDR regime. It is shown that conductivity modulation is a necessary but not sufficient condition for the occurrence of negative resistance in SA-LIGBT devices. Also required is a large voltage drop in the high-resistivity drift region before conductivity modulation is initiated. This causes small changes in the anode current level, greatly decreasing the total resistance across the drift region     

Large enhancement of interband tunneling current densities of over105 A/cm2 inIn0.53Ga0.47As-based surface tunnel transistors

In_0.53Ga_0.47As-based Surface Tunnel Transistors (STT's), which control an interband tunneling current between an n-type channel and a p-type drain by an insulated gate, are investigated with the goal of increasing the tunneling current-density for high-speed operation. The fabricated devices enhanced an interband tunneling current density by a factor of 10² compared to the conventional GaAs-STT's due to a smaller bandgap energy and a lighter electron effective mass, and exhibited a clear gate-controlled negative differential resistance (NDR) characteristics with maximum tunneling current densities of over 10⁵ A/cm². The cutoff frequency (F_T) and maximum oscillation frequency (f_max ) of a fabricated device with a 1.0-μm gate length were estimated to be 7.9 GHz and 20 GHz, respectively, in the NDR region     

Device simulation of submicrometer gate p+-i-p+ diamond transistors

Two-dimensional device simulation of submicrometer gate diamond p ⁺-i-p⁺ transistors with a SiO₂ gate insulator was investigated using the MEDICI device simulation program. A large modulation of the source-to-drain current was obtained in the accumulation mode. The computed diamond device characteristics were equivalent or better than the simulation results of 6H-SiC MESFET's. It was concluded that the problems in diamond MESFET associated with the deep acceptor levels due to boron doping can be overcome in the p⁺ -i-p⁺ diamond FET's because of the hole injection and the space charge limited current     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Modeling CMOS tunneling currents through ultrathin gate oxide dueto conduction- and valence-band electron and hole tunneling

A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N⁺, P⁺ , Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-gate poly-Si_1-xGe_x-gated (x=0 or 0.25) CMOS devices for various gate oxide thicknesses. In addition, this model ran also be employed to determine the physical oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current)     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

The effect of native oxide on thin gate oxide integrity

We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using HF-vapor treated and H₂ baked processes. Furthermore, an extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm² and a large charge injection of 7.9×10⁴ C/cm². The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole traps     

Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions     

N-shaped negative differential resistance in a transistor structurewith a resistive gate

Voltage-controlled negative differential resistance (NDR) characteristics in a N-AlGaAs/p⁺-GaAs/n-GaAs transistor structure are proposed and demonstrated. The gate, made using self-aligned p-type diffusion, is placed in the n-GaAs collector layer instead of the p⁺-GaAs base layer, resulting in a so-called resistive gate. For a fixed gate voltage, the device current is modulated by the applied anode voltage. Under appropriate gate voltage with respect to the anode, the device shows good voltage-controllable NDR characteristics, including large peak-to-valley current ratios (PTV's) and a voltage extension in the N-shaped curve which is equivalent to the common-emitter breakdown voltage in a transistor. A numerical model based on the transistor model for the carrier transport in this device, taking account of the influence of the applied anode voltage on the gate, is proposed. The experimental results show large room temperature PTV's (e.g., 140 at a gate bias of 1.5 V) and large voltage extension in N-shaped curves (about 9 V). Reasonable agreement between theoretical and experimental results is observed     

Sub-1/4-μm dual-gate CMOS technology using in-situ dopedpolysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage     

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n⁺ polysilicon gate, and p⁺ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm²/V-s at 300 K and 980 cm²/V-s at 82 K were achieved in functional submicrometer p-MOSFETs     

Quantum-well p-channel AlGaAs/InGaAs/GaAs heterostructureinsulated-gate field-effect transistors with very high transconductance

Quantum-well p-channel pseudomorphic AlGaAs/InGaAs/GaAs heterostructure insulated-gate field-effect transistors with enhanced hole mobility are described. The devices exhibit room-temperature transconductance, transconductance parameter, and maximum drain current as high as 113 mS/mm, 305 mS/V/mm, and 94 mA/mm, respectively, in 0.8-μm-gate devices. Transconductance, transconductance parameter, and maximum drain current as high as 175 mS/mm, 800 mS/V/mm, and 180 mA/mm, respectively were obtained in 1-μm p-channel devices at 77 K. From the device data hole field-effect mobilities of 860 cm²/V-s at 300 K and 2815 cm²/V-s at 77 K have been deduced. The gate current causes the transconductance to drop (and even to change sign) at large voltage swings. Further improvement of the device characteristics may be obtained by minimizing the gate current. To this end, a type of device structure called the dipole heterostructure insulated-gate field-effect transistor is proposed     

A GSMBE grown GaInP/GaAs narrow base DHBT exhibiting N-shapenegative differential resistance with variable peak-to-valley currentratio up to 1×107 at room temperature

A Ga_0.51In_0.49P/GaAs DHBT with a heavily doped (1×10¹⁹ cm^-3) narrow base (8 nm) grown by gas source molecular beam epitaxy and fabricated by simple wet chemical etching was demonstrated for the first time. A variable “N” shape negative differential resistance (NDR) controlled by base current was observed in the common-emitter current-voltage characteristics of this device at room temperature. A maximum peak-to-valley current ratio of 1×10⁷ and a maximum current gain of 83 were achieved at room temperature. The largest peak-to-valley current ratio (1×10⁷) achieved is, to our knowledge, the highest reported value to date. The NDR characteristics were explained by the base resistance effect     

Diamond thin-film recessed gate field-effect transistors fabricatedby electron cyclotron resonance plasma etching

A new technique for etching boron-doped homoepitaxial diamond films was used to fabricate mesa-isolated recessed gate field-effect transistors that operate at temperatures up to 350°C. The upper temperature range is limited by the gate leakage current. The room-temperature hole concentration and mobility of the diamond film active layer were 1.2×10¹³ cm^-3 and 280 cm ²/V-s, respectively. The maximum transconductance was 87 μS/mm at 200°C     

A New InP/InGaAs Double Heterojunction Bipolar Transistor With a Step-Graded InAlGaAs Collector Structure

An interesting InP/InGaAs double heterojunction bipolar transistor with a step-graded InAlGaAs layer at the base-collector (B-C) heterojunction is fabricated and studied. Simulated results reveal that the potential spike at the B-C heterointerface is completely eliminated. Experimentally, the operation regime is wider than 11 decades in magnitude of the collector current (I_c = 10^-12 A to I_c = 10^-1 A). Furthermore, the studied device exhibits a relatively high common-emitter breakdown voltage and low output conductance even at high temperature. In the microwave characteristics, the unity current gain cutoff frequency f_T = 72.7 GHz and the maximum oscillation frequency f _max = 50 GHz are achieved for a nonoptimized device (A_E = 6 times 6 mum²).     

All-GaAs/AlGaAs readout circuit for quantum-well infrared detectorfocal plane array

We report the fabrication and testing of an all-GaAs/AlGaAs hybrid readout circuit operating at 77 K designated for use with an GaAs/AlGaAs background-limited quantum-well infrared photodetector focal plane array (QWIP FPA). The circuit is based on a direct injection scheme, using specially designed cryogenic GaAs/AlGaAs MODFET's and a novel n⁺ -GaAs/AlGaAs/n⁺-GaAs semiconductor capacitor, which is able to store more than 15 000 electrons/μm² in a voltage range of ±0.7 V. The semiconductor capacitor shows little voltage dependence, small frequency dispersion, and no hysteresis. We have eliminated the problem of low-temperature degradation of the MODFET I-V characteristics and achieved very low gate leakage current of about 100 fA in the subthreshold regime. The MODFET electrical properties including input-referred noise voltage and subthreshold transconductance were thoroughly tested. Input-referred noise voltage as low as 0.5 μV/√Hz at 10 Hz was measured for a 2×30 μm² gate MODFET. We discuss further possibilities for monolithic integration of the developed devices     

High-speed p+ GaInAs-n InP heterojunction JFET's(HJFET's) grown by MOCVD

The authors report the high-frequency characteristics of a new type of InP-JFET having p⁺ GaInAs as the gate material grown by MOCVD (metalorganic chemical vapor deposition) using tertiarybutylphosphine (TBP) and tertiarybutylarsine (TBA) as the alternative source for phosphine and arsine, respectively. Using selective wet chemical etching, heterojunction JFETs (HJFETs) with gate length of 0.6 μm led to a unity current gain cutoff frequency and power gain cutoff frequency of 14.3 and 37.5 GHz, respectively. The large valence band discontinuity (▵E_v≈0.37 eV) considerably suppresses hole injection into the channel in the HJFET as compared to homojunction InP-JFETs, making the HJFET a preferred device for high-speed logic circuits based on JFET technology     

SiGe pMOSFET's with gate oxide fabricated by microwave electroncyclotron resonance plasma processing

A new process, electron cyclotron resonance (ECR) microwave plasma oxidation, has been developed to produce a gate-quality oxide directly on SiGe alloys. One μm Al gate Si_0.86Ge_0.15 p-metal-oxide-semiconductor field-effect-transistors (pMOSFET's) with ECR-grown gate oxide have been fabricated. It is found that saturation transconductance increases from 48 mS/mm at 300 K to 60 mS/mm at 77 K. Low field hole mobilities of 167 cm²/V-s at 300 K and 530 cm ²/V-s at 77 K have been obtained     

Effects of avalanche hole injection in fluorinated SiO2MOS capacitors

Significantly improved immunity to hot-hole damage of the SiO₂/Si structure is achieved by a shallow fluorine implantation into the poly-Si gate of MOS capacitors followed by a drive-in process. Compared to the nonfluorinated control, the fluorinated samples exhibit a dramatic reduction of both hole trapping probability and interface-trap generation under avalanche hole injection conditions. The degree of such an improvement increases monotonically as a function of the F implantation dose (up to 10¹⁶/cm² ). Significant decrease of the hole detrapping rate is also observed in fluorinated samples. Possible mechanisms are discussed     

Hot hole gate current in surface channel PMOSFETs

This paper reports the observation of a new hot hole component of the gate current of p⁺-poly gate pMOS transistors. The phenomenon is characterized as a function of drain, gate, and substrate bias on devices featuring different oxide thickness and drain engineering options. The new hole gate current component is ascribed to injection into the oxide of substrate tertiary holes, generated by an impact ionization feedback mechanism similar to that responsible of CHannel Initiated Secondary ELectron injection (CHISEL) in nMOSFETs