Top-gated chemical vapor deposition grown graphene transistors with current saturation

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.     

State-of-the-art graphene high-frequency electronics

High-performance graphene transistors for radio frequency applications have received much attention and significant progress has been achieved. However, devices based on large-area synthetic graphene, which have direct technological relevance, are still typically outperformed by those based on mechanically exfoliated graphene. Here, we report devices with intrinsic cutoff frequency above 300 GHz, based on both wafer-scale CVD grown graphene and epitaxial graphene on SiC, thus surpassing previous records on any graphene material. We also demonstrate devices with optimized architecture exhibiting voltage and power gains reaching 20 dB and a wafer-scale integrated graphene amplifier circuit with voltage amplification.     

Self-Aligned, Extremely High Frequency III-V Metal-Oxide-Semiconductor Field-Effect Transistors on Rigid and Flexible Substrates

This paper reports the radio frequency (RF) performance of InAs nanomembrane transistors on both mechanically rigid and flexible substrates. We have employed a self-aligned device architecture by using a T-shaped gate structure to fabricate high performance InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with channel lengths down to 75 nm. RF measurements reveal that the InAs devices made on a silicon substrate exhibit a cutoff frequency (f(t)) of ～165 GHz, which is one of the best results achieved in III-V MOSFETs on silicon. Similarly, the devices fabricated on a bendable polyimide substrate provide a f(t) of ～105 GHz, representing the best performance achieved for transistors fabricated directly on mechanically flexible substrates. The results demonstrate the potential of III-V-on-insulator platform for extremely high-frequency (EHF) electronics on both conventional silicon and flexible substrates.     

High-frequency graphene voltage amplifier

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ～5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.     

Epitaxial graphene transistors: enhancing performance via hydrogen intercalation

We directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. Upon successful buffer elimination, carrier mobility increases from an average of 800 cm(2)/(V s) to >2000 cm(2)/(V s). Additionally, graphene transistor current saturation increases from 750 to >1300 mA/mm, and transconductance improves from 175 mS/mm to >400 mS. Finally, we report a 10× improvement in the extrinsic current gain response of graphene transistors with optimal extrinsic current-gain cutoff frequencies of 24 GHz.     

Current saturation and voltage gain in bilayer graphene field effect transistors

The emergence of graphene with its unique electrical properties has triggered hopes in the electronic devices community regarding its exploitation as a channel material in field effect transistors. Graphene is especially promising for devices working at frequencies in the 100 GHz range. So far, graphene field effect transistors (GFETs) have shown cutoff frequencies up to 300 GHz, while exhibiting poor voltage gains, another important figure of merit for analog high frequency applications. In the present work, we show that the voltage gain of GFETs can be improved significantly by using bilayer graphene, where a band gap is introduced through a vertical electric displacement field. At a displacement field of -1.7 V/nm the bilayer GFETs exhibit an intrinsic voltage gain up to 35, a factor of 6 higher than the voltage gain in corresponding monolayer GFETs. The transconductance, which limits the cutoff frequency of a transistor, is not degraded by the displacement field and is similar in both monolayer and bilayer GFETs. Using numerical simulations based on an atomistic p(z) tight-binding Hamiltonian we demonstrate that this approach can be extended to sub-100 nm gate lengths.     

Radio frequency transistors based on ultra-high purity semiconducting carbon nanotubes with superior extrinsic maximum oscillation frequency

In this paper, we report polyfluorene-separated ultra-high purity semiconducting carbon nanotube radio frequency transistors with a self-aligned T-shape gate structure. Because of the ultra-high semiconducting tube purity and self-aligned T-shape gate structure, these transistors showed an excellent direct current and radio frequency performance. In regard to the direct current characteristics, these transistors showed a transconductance up to 40 μS/μm and an excellent current saturation behavior with an output resistance greater than 200 kΩ·μm. In terms of the radio frequency characteristics, an extrinsic maximum oscillation frequency (f _max) of 19 GHz was achieved, which is a record among all kinds of carbon nanotube transistors, and an extrinsic current gain cut-off frequency (f _T) of 22 GHz was achieved, which is the highest among transistors based on carbon nanotube networks. Our results take the radio frequency performance of carbon nanotube transistors to a new level and can further accelerate the application of carbon nanotubes for future radio frequency electronics.

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Flexible gigahertz transistors derived from solution-based single-layer graphene

Flexible electronics mostly relies on organic semiconductors but the limited carrier velocity in polymers and molecular films prevents their use at frequencies above a few megahertz. Conversely, the high potential of graphene for high-frequency electronics on rigid substrates was recently demonstrated. We conducted the first study of solution-based graphene transistors at gigahertz frequencies, and we show that solution-based single-layer graphene ideally combines the required properties to achieve high speed flexible electronics on plastic substrates. Our graphene flexible transistors have current gain cutoff frequencies of 2.2 GHz and power gain cutoff frequencies of 550 MHz. Radio frequency measurements directly performed on bent samples show remarkable mechanical stability of these devices and demonstrate the advantages of solution-based graphene field-effect transistors over other types of flexible transistors based on organic materials.     

Scalable templated growth of graphene nanoribbons on SiC

In spite of its excellent electronic properties, the use of graphene in field-effect transistors is not practical at room temperature without modification of its intrinsically semimetallic nature to introduce a bandgap. Quantum confinement effects can create a bandgap in graphene nanoribbons, but existing nanoribbon fabrication methods are slow and often produce disordered edges that compromise electronic properties. Here, we demonstrate the self-organized growth of graphene nanoribbons on a templated silicon carbide substrate prepared using scalable photolithography and microelectronics processing. Direct nanoribbon growth avoids the need for damaging post-processing. Raman spectroscopy, high-resolution transmission electron microscopy and electrostatic force microscopy confirm that nanoribbons as narrow as 40 nm can be grown at specified positions on the substrate. Our prototype graphene devices exhibit quantum confinement at low temperatures (4 K), and an on-off ratio of 10 and carrier mobilities up to 2,700 cm(2) V(-1) s(-1) at room temperature. We demonstrate the scalability of this approach by fabricating 10,000 top-gated graphene transistors on a 0.24-cm(2) SiC chip, which is the largest density of graphene devices reported to date.     

Extremely bendable, high-performance integrated circuits using semiconducting carbon nanotube networks for digital, analog, and radio-frequency applications

Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns the organic semiconductor materials. In this work, we report the use of semiconductor-enriched carbon nanotubes for high-performance integrated circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance with on-current and transconductance up to 15 μA/μm and 4 μS/μm. By performing capacitance-voltage measurements, the gate capacitance of the nanotube TFT is precisely extracted and the corresponding peak effective device mobility is evaluated to be around 50 cm(2)V(-1)s(-1). Using such devices, digital logic gates including inverters, NAND, and NOR gates with superior bending stability have been demonstrated. Moreover, radio frequency measurements show that cutoff frequency of 170 MHz can be achieved in devices with a relatively long channel length of 4 μm, which is sufficient for certain wireless communication applications. This proof-of-concept demonstration indicates that our platform can serve as a foundation for scalable, low-cost, high-performance flexible electronics.     

Chemical vapor deposition-derived graphene with electrical performance of exfoliated graphene

While chemical vapor deposition (CVD) promises a scalable method to produce large-area graphene, CVD-grown graphene has heretofore exhibited inferior electronic properties in comparison with exfoliated samples. Here we test the electrical transport properties of CVD-grown graphene in which two important sources of disorder, namely grain boundaries and processing-induced contamination, are substantially reduced. We grow CVD graphene with grain sizes up to 250 μm to abate grain boundaries, and we transfer graphene utilizing a novel, dry-transfer method to minimize chemical contamination. We fabricate devices on both silicon dioxide and hexagonal boron nitride (h-BN) dielectrics to probe the effects of substrate-induced disorder. On both substrate types, the large-grain CVD graphene samples are comparable in quality to the best reported exfoliated samples, as determined by low-temperature electrical transport and magnetotransport measurements. Small-grain samples exhibit much greater variation in quality and inferior performance by multiple measures, even in samples exhibiting high field-effect mobility. These results confirm the possibility of achieving high-performance graphene devices based on a scalable synthesis process.     

Cascading Wafer-Scale Integrated Graphene Complementary Inverters under Ambient Conditions

The fundamental building blocks of digital electronics are logic gates which must be capable of cascading such that more complex logic functions can be realized. Here we demonstrate integrated graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading. We obtain signal matching under ambient conditions with inverters fabricated from wafer-scale graphene grown by chemical vapor deposition (CVD). Monolayer graphene was incorporated in self-aligned field-effect transistors in which the top gate overlaps with the source and drain contacts. This results in full-channel gating and leads to the highest low-frequency voltage gain reported so far in top-gated CVD graphene devices operating in air ambient, A(v) ～ -5. Such gain enabled logic inverters with the same voltage swing of 0.56 V at their input and output. Graphene inverters could find their way in realistic applications where high-speed operation is desired but power dissipation is not a concern, similar to emitter-coupled logic.     

Large-scale graphene transistors with enhanced performance and reliability based on interface engineering by phenylsilane self-assembled monolayers

In this letter, we report the dielectric/graphene interface physics and engineering of large-scale, chemical vapor deposited (CVD) graphene transistors by self-assembling a molecular-scale organosilane monolayer onto the dielectric surface. We show that phenyl-alkyl-terminated self-assembled monolayers (SAM) at the dielectric/graphene interface consistently improve the graphene device performance and reliability. The extrinsic field-effect mobility of large-scale CVD graphene transistors on the phenyl-SAM engineered dielectric is currently up to 2500 cm(2)/(V s) at room temperature, considerably higher than the counterparts without the SAM. In addition, significant reduction on the bias stress instability and hysteresis is achieved by the SAM-based interface engineering. Further analysis reveals that charge injection from graphene to the dielectric/graphene interface dominates the observed hysteresis behavior. For both graphene transistors with and without SAMs, the bias stress stability, that is, Dirac point shift under bias stress, is well described by the stretched exponential model with its fitting parameters clearly indicating different interface properties.     

Graphene as a tunnel barrier: graphene-based magnetic tunnel junctions

Graphene has been widely studied for its high in-plane charge carrier mobility and long spin diffusion lengths. In contrast, the out-of-plane charge and spin transport behavior of this atomically thin material have not been well addressed. We show here that while graphene exhibits metallic conductivity in-plane, it serves effectively as an insulator for transport perpendicular to the plane. We report fabrication of tunnel junctions using single-layer graphene between two ferromagnetic metal layers in a fully scalable photolithographic process. The transport occurs by quantum tunneling perpendicular to the graphene plane and preserves a net spin polarization of the current from the contact so that the structures exhibit tunneling magnetoresistance to 425 K. These results demonstrate that graphene can function as an effective tunnel barrier for both charge and spin-based devices and enable realization of more complex graphene-based devices for highly functional nanoscale circuits, such as tunnel transistors, nonvolatile magnetic memory, and reprogrammable spin logic.     

Wafer‐Scale Patterning of Reduced Graphene Oxide Electrodes by Transfer‐and‐Reverse Stamping for High Performance OFETs

A wafer‐scale patterning method for solution‐processed graphene electrodes, named the transfer‐and‐reverse stamping method, is universally applicable for fabricating source/drain electrodes of n‐ and p‐type organic field‐effect transistors with excellent performance. The patterning method begins with transferring a highly uniform reduced graphene oxide thin film, which is pre‐prepared on a glass substrate, onto hydrophobic silanized (rigid/flexible) substrates. Patterns of the as‐prepared reduced graphene oxide films are then formed by modulating the surface energy of the films and selectively delaminating the films using an oxygen‐plasma‐treated elastomeric stamp with patterns. Reduced graphene oxide patterns with various sizes and shapes can be readily formed onto an entire wafer. Also, they can serve as the source/drain electrodes for benchmark n‐ and p‐type organic field‐effect transistors with enhanced performance, compared to those using conventional metal electrodes. These results demonstrate the general utility of this technique. Furthermore, this simple, inexpensive, and scalable electrode‐patterning‐technique leads to assembling organic complementary circuits onto a flexible substrate successfully.     

Control and characterization of individual grains and grain boundaries in graphene grown by chemical vapour deposition

The strong interest in graphene has motivated the scalable production of high-quality graphene and graphene devices. As the large-scale graphene films synthesized so far are typically polycrystalline, it is important to characterize and control grain boundaries, generally believed to degrade graphene quality. Here we study single-crystal graphene grains synthesized by ambient chemical vapour deposition on polycrystalline Cu, and show how individual boundaries between coalescing grains affect graphene's electronic properties. The graphene grains show no definite epitaxial relationship with the Cu substrate, and can cross Cu grain boundaries. The edges of these grains are found to be predominantly parallel to zigzag directions. We show that grain boundaries give a significant Raman 'D' peak, impede electrical transport, and induce prominent weak localization indicative of intervalley scattering in graphene. Finally, we demonstrate an approach using pre-patterned growth seeds to control graphene nucleation, opening a route towards scalable fabrication of single-crystal graphene devices without grain boundaries.     

Gigahertz Electromagnetic Structures via Direct Ink Writing for Radio‐Frequency Oscillator and Transmitter Applications

Radio‐frequency (RF) electronics, which combine passive electromagnetic devices and active transistors to generate and process gigahertz (GHz) signals, provide a critical basis of ever‐pervasive wireless networks. While transistors are best realized by top‐down fabrication, relatively larger electromagnetic passives are within the reach of printing techniques. Here, direct writing of viscoelastic silver‐nanoparticle inks is used to produce a broad array of RF passives operating up to 45 GHz. These include lumped devices such as inductors and capacitors, and wave‐based devices such as transmission lines, their resonant networks, and antennas. Moreover, to demonstrate the utility of these printed RF passive structures in active RF electronic circuits, they are combined with discrete transistors to fabricate GHz self‐sustained oscillators and synchronized oscillator arrays that provide RF references, and wireless transmitters clocked by the oscillators. This work demonstrates the synergy of direct ink writing and RF electronics for wireless applications.     

Solution‐Processed Ti3C2Tx MXene Antennas for Radio‐Frequency Communication

Highly integrated, flexible, and ultrathin wireless communication components are in significant demand due to the explosive growth of portable and wearable electronic devices in the fifth‐generation (5G) network era, but only conventional metals meet the requirements for emerging radio‐frequency (RF) devices so far. Here, it is reported on Ti₃C₂T_x MXene microstrip transmission lines with low‐energy attenuation and patch antennas with high‐power radiation at frequencies from 5.6 to 16.4 GHz. The radiation efficiency of a 5.5 µm thick MXene patch antenna manufactured by spray‐coating from aqueous solution reaches 99% at 16.4 GHz, which is about the same as that of a standard 35 µm thick copper patch antenna at about 15% of its thickness and 7% of the copper weight. MXene outperforms all other materials evaluated for patch antennas to date. Moreover, it is demonstrated that an MXene patch antenna array with integrated feeding circuits on a conformal surface has comparable performance with that of a copper antenna array at 28 GHz, which is a target frequency in practical 5G applications. The versatility of MXene antennas in wide frequency ranges coupled with the flexibility, scalability, and ease of solution processing makes MXene promising for integrated RF components in various flexible electronic devices.     

Downscaling of self-aligned, all-printed polymer thin-film transistors

Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poor resolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages. Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100-400 nm. The use of a crosslinkable polymer gate dielectric with 30-50 nm thickness ensures that basic scaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistance effects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasitic overlap capacitance to values as low as 0.2-0.6 pF mm(-1), and allows transition frequencies of fT = 1.6 MHz to be reached. Our self-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, while remaining compatible with the requirements of large-area, flexible electronics manufacturing.     

Ultrahigh Frequency Carbon Nanotube Transistor Based on a Single Nanotube

Single-walled carbon nanotube field-effect transistors (CNT FETs) are predicted to have intrinsic cutoff frequencies approaching the THz range. Here ldquointrinsicrdquo means that the parasitic capacitance due to fringing fields is negligible compared to the gate-source capacitance required to modulate the conductance. In practice, although there are strategies proposed to mitigate this based on parallel arrays of CNT FETs, this parasitic capacitance dominates most geometries (even aligned arrays to date). In this work we show nanotube transistor performance with maximum stable gain above 1 GHz (even including the parasitics) by combining ldquoon-chiprdquo the electrical properties of 100 CNT FETs fabricated on one long nanotube. This also solves the problem of impedance matching by boosting the on current to a large (mA) value, and at the same time allows one to extract properties of each individual CNT FET, since they are identical in electrical characteristics as they are made out of the same CNT. This strategy opens the door to applications of carbon nanotube devices in the RF and microwave frequency range, a technologically relevant portion of the spectrum for both wired and wireless electronics, that has been (until now) incompatible with nanotube device technology.