Lower bounds for q-ary covering codes

The authors prove combinatorial lower bounds for K_q (n,R), the minimal cardinality of any q-ary code of length n and covering radius R. Tables of lower bounds for K_q(n,R) are presented for q=3, 4, 5     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs

The usual approximate expression for measured f_T =[g_m/2π (C_gs+C _gd)] is inadequate. At low drain voltages just beyond the knee of the DC I-V curves, where intrinsic f _t is a maximum for millimeter-wave MODFETs, the high values of C_gd and G_ds combine with the high g_m to make terms involving the source and drain resistance significant. It is shown that these resistances can degrade the measured f_T of a 0.30-μm GaAs-AlGaAs MODFET from an intrinsic maximum f_T value of 73 GHz to a measured maximum value of 59 GHz. The correct extraction of maximum f_T is essential for determining electron velocity and optimizing low-noise performance     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

In0.52Al0.48As/InxGa1-xAs (0.53⩽x⩽0.70) lattice-matched and strainedheterostructure insulated-gate FETs

The DC and microwave properties of In_0.52Al_0.48 Al/In_xGa_1-xAs (0.53⩽x⩽0.70) heterostructure insulated gate field-effect transistors (HIGFETs) with a quantum well channel design are presented. DC and microwave transconductances (g_m) are enhanced as the In content is increased in the InGaAs channel. An intrinsic microwave g _m value of 428 mS/mm and a K-factor of 1140 mS/mm-V have been obtained for 1.0-μm gate length with the 65% In channel devices. The sheet charge density, drift mobility, transconductance, current-gain cutoff frequency (f_T), and maximum oscillation frequency (f _max) all show a continuous improvement up to 65% In content ( f_T=22.5 GHz with 53% and f_T=27 GHz with 65% In; the corresponding f_max change is from 6.5 to 8 GHz). The device performance degrades as the In content is increased to 70%. DC and microwave characteristics show the presence of negative differential resistance (NDR) up to 2.7 GHz     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

An input-free VT extractor circuit using atwo-transistor differential amplifier

A three-terminal circuit (power, ground, and output) that provides a DC output voltage equal to the MOS threshold voltage V_T is presented. The circuit uses the four-terminal extractor topology of Z. Wang (1992), but it adds self-biasing and a two-transistor differential amplifier to provide a ground-referenced output voltage     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

A pseudomorphic AlGaAs/n+-InGaAs metal-insulator-dopedchannel FET for broad-band, large-signal applications

Molecular beam epitaxy (MBE)-grown L_g=1.7-μm pseudomorphic Al_0.38Ga_0.62As/n⁺-In_0.15Ga _0.85As metal-insulator-doped channel FETs (MIDFETs) are presented that display extremely broad plateaus in both f_T and f_max versus V_GS, with f_T sustaining 90% of its peak over a gate swing of 2.6 V. Drain current is highly linear with V_GS over this swing, reaching 514 mA/mm. No frequency dispersion in g _m up to 3 GHz was found, indicating the absence of electrically active traps in the undoped AlGaAs pseudoinsulator layer. These properties combine to make the pseudomorphic MIDFET highly suited to linear, large-signal, broadband applications     

Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Confidence bounds for Pr{X>Y} in 1-way ANOVArandom model

Approximate confidence bounds for reliability, R=Pr{X >Y|X,Y}, are obtained, where X and Y are independent normal (Gaussian) random variables, and X and Y are vectors of measurements for X and Y, respectively. Balanced 1-way ANOVA (analysis of variants) random effect models are assumed for the populations of X and Y. Confidence bounds are derived for R under three cases for standard deviations, σ_x and σ_y. An example shows how the results are used     

Correlation between 1/f noise and hFElong-term instability in silicon bipolar devices

Accelerated life tests with high-temperature storage and electric aging for n⁺-p-n silicon planar transistors were carried out. Current gain h_FE increases monotonously with time during the tests, and the h_FE drift is correlated with initial measured 1/f noise in the transistors, i.e. the drift amount significantly increases with the increase of noise level. The correlation coefficient of relative drift Δh_FE /h_FE and 1/f noise spectral density S_iB(f) is far larger than that of Δ h_FE/h_FE and initial DC parameters of the transistors. A quantitative theory model for the h _FE drift has been developed and explains the h _FE drift behavior in the tests, which suggests that the h _FE drift and 1/f noise can be attributed to the same physical origin, and both are caused by the modulation of the oxide traps near the Si-SiO₂ interface to Si surface recombination. 1/f noise measurement, therefore, may be used as a fast and nondestructive means to predict the long-term instability in bipolar transistors     

The total PFA of the multiwindow harmonicdetector and its application to real data

The authors study the multiwindow spectral analysis method as it applies to the detection of sinusoidal signals. They examine the probability of false alarm P_FA. The total P _FA (sinusoidal frequency unknown) is shown analytically to be bounded below by the order statistics (minimum) of BM/K independent identically distributed (i.i.d.) beta variates, where M is the length of the data record used in the detection, K the number of windows, and B the width of the frequency band of interest. Simulation results indicate a much larger bound, the minimum of BM i.i.d. beta variates. It is shown that for real signals, the assumptions made in the derivation of the detector break down at frequencies close to zero and to half the sampling frequency     

m-consecutive-k-out-of-n:F systems

An m-consecutive-k-out-of-n:F system, consists of n components ordered on a line; the system fails if and only if there are at least m nonoverlapping runs of k consecutive failed components. Three theorems concerning such systems are stated and proved. Theorem one is a recursive formula to compute the failure probability of such a system. Theorem two is an exact formula for the failure probability. Theorem three is a limit theorem for the failure probability     

Low-frequency noise characteristics of lattice-matched(x=0.53) and strained (x>0.53) In0.52Al0.48As/InxGa1-xAs HEMT's

Extensive bias-dependent and temperature-dependent low-frequency (LF) noise measurements were performed on lattice-matched and strained In_0.52Al_0.48As/In_xGa_1-x As(0.53<x<0.70) HEMTs. The input-noise voltage spectra density is insensitive to V_DS bias and shows a minimum at V_GS corresponding to the peak g_m condition. The corresponding output-noise voltage spectral density, which depends strongly on the gain of the devices, increases with V_DS. The input noise was rather insensitive to indium (In) content. Temperature-dependent low-frequency noise measurements on these devices reveal shallow traps with energies of 0.11, 0.15, and 0.18 eV for 60%, 65%, and 70% In HEMTs. Noise transition frequencies for these devices were on the order of 200-300 MHz and remain almost the same for different channel In content and V_DS bias     

A technique for real-time measurement of Nth-orderderivativesdNV/dIN

A technique for the measurement of device derivatives d ^NV/dI^N of arbitrary order N described. Measurement is accomplished by injecting a test current composed of the sum of N square waves into the rest device, and then multiplying the corresponding voltage change by the product of those same square waves, followed by low-pass filtering. The algorithm is implemented in real time using a mixture of analog and digital circuitry, and its application to semiconductor laser control in high-speed optical communications is described     

Bias dependence of fT and fmax in anIn0.52Al0.48As/n+-In0.53Ga0.47As MISFET

Detailed microwave characterization of a recently fabricated In _0.52Al_0.48As/n⁺-In_0.53Ga _0.47As MISFET reveals that high values of current-gain cutoff frequency (f_T) and unilateral-gain cutoff frequency (f_max) are obtained for a broad range of gate bias voltage values. A significant peak in f_T and f _max has also been observed at high gate-source bias values. The peak coincides with the onset of electron accumulation at the heterointerface and is attributed to reduced ionized impurity scattering coupled with reduced drain conductance. This result suggests an improved device structure that optimizes operation in the accumulation regime     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation